1. 針對高速介面進行信號完整性模擬。
SI simulation : TDR, S parameter,Eye diagram,Crosstalk..
2. 電路板電源完整性模擬。
PI simulation : IR Drop , PDN..
3. 對於佈局圖給予改良建議。
Polar應用及評估PCB & VNA材料選擇方式
4. 信號完整性異常除錯。
Summary:
Part of design automation team to enable and verify Printed Circuit Board (PCB) hardware and layout designs.
Essential Duties and Responsibilities:
• Execute Power Integrity (PI) tools and provide inputs to design and lab teams
• Execute Signal Integrity (SI) tools and provide inputs to design and lab teams
• Develop scripts to provide solutions in design and PCB manufacturing issues
• Define and develop design methodologies to improve design quality and productivity
• Engage with Computer Aided Design (CAD) tool vendors for tool evaluation and support
• Engage with PCB and CM vendors to understand and evaluate PCB materials and stackups
1.PCB stack-up design & Constraint Rule setting.
2.Provide SI/PI design suggestions for PCB layout.
3.Signal integrity analysis of high-speed and low-speed signal interfaces.
4.Power integrity design includes DC impedance, AC resonance and capacitance optimization.
5.In addition to Cadence 2.5D EM solution as a daily necessary software, AMD SeaSim/S2Eye, Intel ICAT/IMLC/CCT are also required.
6.Use TCL and Python to shorten the complicated software operation process, generate reports and perform DOE analysis.
7.Familiar with PCB test coupon TDR/TDT measurement and Delta L 4.0 Measurement.
Purpose of this Position
深入研究高速訊號,在高速硬體電路Signal Integrity上提供最佳設計且確保生產品質
Major Areas of Responsibility
專案研發
- Perform high speed signal integrity simulation including 10G/40G、25G/100G、PCIE、SATA、DP、USB、DDR3/DDR4/DDR5.
- Perform pre-layout, layout constraint, and post-layout simulation processes.
- PCB stackup design and layout review for high speed signal and PDN.
- Build component models to ensure the correlation between SI/PI simulation and measurement.
- Solid SI experience in resolving technical issues and performing detailed analysis.
團隊合作
- Collaborating with EE teams to refine high-speed signal performance.
- Collaborate with the layout engineer to provide clear layout guidelines and enhance footprint optimization.
1.Cable related product line set up into assigned location
2.Drive the cost reduction to be competitive for expanding into new business
3.Develop and implement product business plan with market, industries and customers targets.
4.Gain new opportunities for industrial cable market , especially on ESS and Robot application , create the USD 20M revenue
5.Promote the CMIO product for industrial market segment
【產品範疇】
1.DDI / TP / TDDI/ TCON/ Power等顯示相關產品
【工作內容】
1. SI/PI/EM issue solving, performance optimization, and design rule development
2. Chip/PKG/Board simulation and measurement for SI/PI/EM issue.
3. Co-work with system engineers, IC designers, and customers on product design-in tasks.