「Verification Engineer」的相似工作

1. Develop the verification plans and build up the verification environment. 2. Coverage hole analysis and improve coverage. 3. Build VIP and test cases 4. Work with RTL design team to debug failing test cases and resolve bugs.

Responsibilities: • Develop integrated verification environment. • Verify designs with system verilog and system verilog assertion. • Build, maintain and upgrade testbenches and their components using UVM-based methods. • Check functional coverage and code coverage • Create controlled random testcases. Pre-debug and provide debug reports. • Scripting experience using scripting languages like Perl and Python.

我們專注於3D影像立體雙目視覺技術 產品應用於3D 影像辨識、360 度環景拍照、攝影或AR 與VR 職務內容： ★ USB2.0/3.1或 MIPI 介面之2D/ 3D 影像處理與壓縮之 IC 開發 ★ 影像處理與壓縮相關數位 IP暨產品之開發設計、測試、驗證 條件要求： 1. 對IP Verification, System Verification 有興趣 2. 熟Verilog coding 與 ASIC design Flow 與 Timing Closure 3. 或有 SoC IC 開發經驗 4. 對開發人工智慧((AI) 晶片與邊緣運算有興趣者

負責DisplayPort產品設計 DisplayPort digital circuit design and verification 工作內容： 1. IC architecture definition 2. Collaborate with analog and system engineers 3. RTL design & verification 4. ASIC & FPGA implementation 5. Customer support and debug 職務條件：(具備下列條件者優先考慮) 1.熟悉USB/PCIe/DisplayPort網路相關經驗 2.具DisplayPort實體層設計與驗證 及 ASIC 經驗 3.熟悉UVM 或有DP VIP使用相關經驗

Product : OLED DDI 1. Develop integrated verification environment. 2. Verify designs with system verilog and system verilog assertion. 3. Develop and optimize verification flow and methodology. 4. Good knowledge of IC design flow. 5. Scripting experience using scripting languages like Perl and Python.

1. Design verification with SystemVerilog/UVM, C/C++ 2. Integration test environment with VIP 3. Develop checker and scoreboard. 4. Verify design with SystemVerilog assertion. 5. Test plan for a verification task. [Requirement] 1. Familiar with SystemVerilog HDL, OOP, Python, TCL, and shell programming. 2. Better to have SoC design and bus concept.

1.客戶FPGA and SoC 技術相關問題處理 2.FPGA and SoC 設計技巧教育訓練 3.Xilinx 產品推廣

【工作內容】 • Work with team members and apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market • Provide the technical leadership to the DV team for the project • Work independently on various DV tasks and provide technical guidance to the DV team. • Be involved technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup 【職務條件】 • Master’s degree in Electrical Engineering, Computer Science, or related. • Good understanding of ASIC design verification flow. • RTL coding with Verilog/System Verilog and familiar with front-end design flow and C/C++ programming experiences. • Knowledge of Perl, OVL, SVA, SV, UVM, OVM, script programming, etc. 【其他條件】 • MSEE with a minimum of 5 years, or BSEE with a minimum of 8 years of experience in digital ASIC/SOC design verification • MS/BS degree in EE or CS with expertise in digital IP/SOC design verification.

1.IP 產品驗證與分析 2.基礎儀器操作使用(示波器/訊號產生器) 3.量測報告製作與整理 4.Python 程式設計與開發

1. 主動式電子掃描陣列 (相控陣列) 雷達系統之數位控制。 2. 熟悉Verilog與FPGA開發流程，了解High-Level Synthesis開發技術。 3. 具有實作數位訊號處理與數位架構設計於FPGA之經驗。

a. Job Description: We are looking for a highly motivated RTL Designer to join our team in developing high-performance digital IPs. The ideal candidate will have experience in Register Transfer Level (RTL) design and verification, with a strong understanding of digital logic, microarchitecture, and ASIC/FPGA development processes. The role involves designing and verifying custom hardware IPs for cutting-edge applications. b. Verification: Develop and execute test plans to verify functionality, performance, and power requirements. Create testbenches using SystemVerilog/UVM for functional verification. Perform simulation, debugging, and root cause analysis for design issues. Conduct code coverage and functional coverage analysis to ensure comprehensive testing. Collaborate with verification and firmware teams to validate IP functionality. c. Qualifications: Bachelor’s/Master’s degree in Electrical Engineering, Computer Engineering, or a related field. 2+ years of experience in RTL design and verification. Proficiency in Verilog, SystemVerilog Strong understanding of digital design concepts, including pipelining, clock domains, and low-power design techniques. Experience with simulation tools (e.g., ModelSim, VCS, Questa) and formal verification techniques. Familiarity with UVM methodology and testbench development. Knowledge of scripting (Python, TCL, Perl, Shell) for automation. Experience with FPGA or ASIC development flows, including synthesis and timing analysis. Strong debugging and problem-solving skills. Excellent communication and teamwork abilities. - Non smoking

(1)Must have BS in CS/EE of relevant experience in IC design field. (2)Familiar with IC design flow, placement and route (P&R), and layout. (3)Circuit knowledge and logic design relevant experience would be a plus.

1. 具 0~2年數位晶片設計，或有 0~5年類比晶片設計工作經驗。 2. 具備基本數位和類比電路知識，熟習標準晶片設計流程。 3. 熟習業界常用EDA tools, 或Matlab/ Simulink。 4. 研習過CMOS or BiCMOS 類比設計電路課程，對放大器有基礎認識。 5. Experience in these areas is preferred： * BiCMOS or CMOS high-speed (>20Gb/s) circuit, Linear electrical amplifier & equalizer, High-speed (>25G) CDR/PLL/SerDes. * Linear optical laser driver & receiver (TIA + linear amplifier) 本職位負責類比IC電路的設計、驗證和除錯。這是一個高度技術性的職位，對公司的產品開發至關重要。我們正在尋找一位熱愛類比IC設計並具有相關經驗的人才，以推動公司的技術創新和發展。 如果您對這個職位感興趣，請投遞您的履歷表，我們立即與您聯繫。

1.Work with team members and apply design techniques to work on different phases of complex logic design for ASIC/SOC project. 2. Working on the following tasks from time to time: HDL coding, documentation, RTL quality check, cooperate with back-end engineer etc.

我們專注於能源晶片與深度演算法的融合創新，誠徵數位IC設計師，加入我們打造次世代電力分析專用SoC晶片的行列，透過數位電路設計與驗證實力，推動能源運算的極致效能與可靠性。 你將負責： ▪️ 設計電力分析專用晶片架構及系統 ▪️ RTL設計與功能驗證，確保系統正確性與效能表現 ▪️ 參與SoC數位區塊的功能設計、整合與驗證 ▪️ 進行綜合、時序分析與低功耗設計優化 我們期待你具備： ▪️ 電子/電機工程學士以上學歷 ▪️ 精通Verilog/SystemVerilog與RTL設計流程 ▪️ 熟悉綜合與時序分析方法 ▪️ 具備DSP演算法硬體實現經驗 ▪️ 理解低功耗設計技術與實務 專業工具： ▪️ Synopsys Design Compiler ▪️ Cadence Genus ▪️ Mentor Graphics 加分條件： ▪️ 具備完整SoC設計專案經驗 ▪️ 熟悉UVM或其他驗證方法學 ▪️ 有28nm以下先進製程設計或量產經驗 ▪️ 具備電力電子或電源管理電路相關背景 如果你熱愛透過數位IC設計挑戰能源晶片的極限，歡迎加入我們，打造更智慧的硬體未來！

1.熟悉數位電路設計及驗證流程 2.熟悉PC架構以及周邊電路設計者尤佳 3.具FPGA經驗 4.Low Power 電路設計 5.溝通能力佳,和其他團隊互動良好

1. SerDes CTRL IP RTL 開發與維護 (例如LPDDR､UFS､NAND Controller...) 2. 設計驗證 3. FPGA相關設計與實作 以上工作依個人意願酌情分配

SoC Peripheral Controller Design and Integration. 包含 PCI-Express Controller, USB Host/Device Controller, Storage Controller (SATA, IDE, SD/MMC), CAN-bus Controller…等等。

【工作內容】 1. 數位電路邏輯控制程式設計 2. 基本通訊界面控制 (UART/I2C/SPGIO/SPI) 3. CPLD規格評估 4. CPLD規格書規劃、撰寫、維護 5. Verilog/VHDL模擬除錯設計 6. CPLD測試、除錯、驗證及最佳化 7. 維護現有CPLD專案 【其他條件&加分項目】 1. 熟悉 Verilog, 2. 若具有 Altera Quartus II, Lattice Diamond , Modelsim能力佳 3. 具有開創性及解決問題的能力 4. 客戶導向及良好溝通技巧 5. 具備推動團隊完成任務的能力 6. 流程管理能力

1.影像應用或訊號處理 IC 研發 2.對數位影像、訊號處理, Verilog/VHDL, 具FPGA design flow 經驗。