「Verification Engineer」的相似工作

【工作內容】 • Work with team members and apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market • Provide the technical leadership to the DV team for the project • Work independently on various DV tasks and provide technical guidance to the DV team. • Be involved technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup 【職務條件】 • Master’s degree in Electrical Engineering, Computer Science, or related. • Good understanding of ASIC design verification flow. • RTL coding with Verilog/System Verilog and familiar with front-end design flow and C/C++ programming experiences. • Knowledge of Perl, OVL, SVA, SV, UVM, OVM, script programming, etc. 【其他條件】 • MSEE with a minimum of 5 years, or BSEE with a minimum of 8 years of experience in digital ASIC/SOC design verification • MS/BS degree in EE or CS with expertise in digital IP/SOC design verification.

We are seeking a highly motivated Design Verification Engineer to join our dynamic team. You will be responsible for ensuring the functional correctness of complex digital designs using industry-leading verification methodologies such as UVM, Formal Verification, and Coverage-Driven Verification. 【Key Responsibilities】 · Develop detailed verification plans based on design specifications and architectural documents. · Build and maintain System Verilog UVM-based testbenches for SoC/Subsystem/IP-level verification. · Write constrained-random and directed test cases to validate functionality, performance, and corner-case scenarios. · Perform coverage analysis (functional coverage, code coverage, assertions coverage) and drive towards coverage closure. · Apply Formal Verification techniques (e.g., property checking, connectivity checking) where applicable. · Support simulation regression runs and maintain automation scripts (Perl/Python/TCL/Makefile). · Participate in design and verification reviews, providing valuable feedback to improve quality.

制定全面的 x86 CPU 驗證計劃，確保驗證流程嚴謹且高效。 規劃並建立 UVM、 Constraint Random、Formal 驗證環境架構，提升驗證效率。 指導與培訓 Junior DV 團隊成員，確保驗證目標的順利達成。

Responsibilities: • Develop integrated verification environment. • Verify designs with system verilog and system verilog assertion. • Build, maintain and upgrade testbenches and their components using UVM-based methods. • Check functional coverage and code coverage • Create controlled random testcases. Pre-debug and provide debug reports. • Scripting experience using scripting languages like Perl and Python.

我們專注於3D影像立體雙目視覺技術 產品應用於3D 影像辨識、360 度環景拍照、攝影或AR 與VR 職務內容： ★ USB2.0/3.1或 MIPI 介面之2D/ 3D 影像處理與壓縮之 IC 開發 ★ 影像處理與壓縮相關數位 IP暨產品之開發設計、測試、驗證 條件要求： 1. 對IP Verification, System Verification 有興趣 2. 熟Verilog coding 與 ASIC design Flow 與 Timing Closure 3. 或有 SoC IC 開發經驗 4. 對開發人工智慧((AI) 晶片與邊緣運算有興趣者

Job Description: In this position the individual will develop test environment, test plan, and test cases based on the product specification and related industrial standards. The individual will require initiating a test plan review with the team and updating the test plan accordingly. The candidate will require executing and developing the test cases based on test plan, debugging and reporting the test result to achieve full function coverage goal. The individual will require developing ASIC bench functional test programs and doing ASIC bring-up and ASIC bench testing. The ideal individual must have proven ability to achieve results in a fast moving, dynamic environment. The candidate must have ability to coordinate priorities and initiatives and clear communication skill.

1. Design verification with SystemVerilog/UVM, C/C++ 2. Integration test environment with VIP 3. Develop checker and scoreboard. 4. Verify design with SystemVerilog assertion. 5. Test plan for a verification task. [Requirement] 1. Familiar with SystemVerilog HDL, OOP, Python, TCL, and shell programming. 2. Better to have SoC design and bus concept.

Job Description We are seeking a highly skilled ASIC Verification Engineer to join our team in Chupei, Taiwan. In this role, you will be responsible for developing and implementing comprehensive verification strategies for complex ASIC designs, ensuring the highest quality and reliability of our semiconductor products. Develop and execute verification plans for complex ASIC designs Create and maintain testbenches using SystemVerilog and UVM Design and implement efficient verification environments Perform functional and formal verification of digital designs Develop automated test scripts to improve verification efficiency Analyze and debug design issues identified during verification Collaborate with design engineers to resolve functional discrepancies Generate detailed verification reports and documentation Stay updated with industry trends and emerging verification methodologies Contribute to the continuous improvement of verification processes and tools Qualifications Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field 5+ years of experience in ASIC verification with strong proficiency in SystemVerilog and UVM Experience with Verilog, VHDL, and industry-standard simulation tools (e.g., Synopsys VCS, Cadence Xcelium) Experience of CPU, GPU, NPU or HBM verification Knowledge of formal verification techniques and tools Strong debugging, problem-solving, and analytical skills Solid understanding of digital logic design, computer architecture, and communication protocols Excellent organizational skills with strong attention to detail Good communication and teamwork skills in a fast-paced environment

- 類比sensor 驗證與除錯與產生驗證報告 - IC datasheet 與技術文件撰寫 - EVB and Test board 設計 - 建立系統模型 - 客戶產品應用支援

使用最新的IC驗證方法對晶心的CPU設計做高強度測試，以提升CPU設計的品質與完整度。此職務可以累積對計算機架構，微架構，與嵌入式系統的廣泛知識。具體內容包含: * Understanding uarch of Andes processor designs * Creating verification plans * Implementing test environments * Generating test cases * Improving test coverage * Identifying CPU bugs in various environments (simulation, FPGA, etc.) * Test automation * Performance benchmarking

- 用Verilog/SystemVerilog撰寫RTL，負責數位電路介面與模擬驗證。 - 參與晶片模組整合與ASIC合成（含DFT、時序收斂）到Tape-out。 - 主導設計專案與SoC整合。 - 帶領小團隊（3人），負責任務分配與技術指導。

1.Integrated verification environment 2.Familiar with SoC level and IP level verification methodology 3.Develop verification plan and optimize verification flow 4.Familiar with verification methodology such as UVM, VMM, or OVM 5.Team player

1. 主動式電子掃描陣列 (相控陣列) 雷達系統之數位控制。 2. 熟悉Verilog與FPGA開發流程，了解High-Level Synthesis開發技術。 3. 具有實作數位訊號處理與數位架構設計於FPGA之經驗。

(1)Must have BS in CS/EE of relevant experience in IC design field. (2)Familiar with IC design flow, placement and route (P&R), and layout. (3)Circuit knowledge and logic design relevant experience would be a plus.

Design CPU functional units. Responsibilities  Defining micro-architecture of the functional units  Writing RTL codes of the functional units  Writing documents of the function units  Working with cross-division teams to resolve functional, performance, power, and frequency issues related to the functional units Qualifications  Available to start work three months after being hired.  3+ years of recent experience with Verilog logic design  Knows CPU micro-architecture, e.g. instructions, pipeline, caches, MMU  Knows power consumption of digital circuits  Good communicator in verbal and writing in English

1. 負責韌體撰寫與維護。 2. 熟悉分析 USB PD 通訊協議。 3. 熟悉分析 USB4、DP2.1、TBT 通訊協議。 4. 客戶服務(Active Cable相關) - 協助客戶釐清技術問題與產品特性分析與測試驗證。 - 具備信號完整性分析，並能進行 Cable 測試與除錯。 5. 具跨部門協作與專案支援能力。 韌體工程師在當今技術發展中扮演了至關重要的角色，他們負責開發和維護公司產品的韌體，並確保其運行穩定。這個職位有著廣闊的發展前景，在未來的技術發展中將會扮演越來越重要的角色。 我們正在尋找有經驗的韌體工程師加入我們的團隊。如果您符合上述要求，請盡快提交您的申請，期待與您合作！

針對數位 IC / SoC / IP 設計進行驗證規劃與測試流程設計。 撰寫驗證計畫 (Testplan)、測試規格與測試案例。 建立與維護 UVM / SystemVerilog 等驗證環境與 testbench。 撰寫 constrained-random / directed testcases，並進行功能覆蓋率 (functional coverage) 與程式碼覆蓋率 (code coverage) 分析。 協助 debug，與設計工程師 (RTL designer) 一同定位與修正問題。 導入並應用 EDA 驗證工具 與跨部門團隊合作，確保設計符合規格與品質。 給新鮮人的你 工作內容: 我們的驗證工程師主要負責確保晶片設計「照著規格跑得正確」。 如果你剛畢業或經驗不多也不用擔心，我們有完整的培訓和資深同事手把手帶領！ 你會接觸到： 學習並建立 晶片驗證環境 (使用 SystemVerilog / UVM)。 撰寫測試案例，模擬晶片設計的各種情境。 分析模擬結果，協助 debug，和設計工程師一起找出問題。 了解 EDA 工具的使用 (simulation、lint、formal 等)。 與團隊合作，確保設計符合規格。 我們希望你具備 (Requirements) 電機、電子、資訊工程或相關科系學士/碩士畢業。 具備 數位電路基礎。 會一點點程式語言 (C/C++、Python、Verilog、SystemVerilog 任一皆可)。 對半導體產業與晶片設計有熱情，願意學習新技術。 樂於團隊合作，遇到問題願意溝通與討論。

1. 熟Verilog及C/C++語言設計。 2. 規劃執行產品韌體之撰寫。 3. 執行、協助或配合韌體新技術之研發、導入。 4. 執行產品韌體測試。

[Responsibilities] ★ Experienced in ISP (Image Signal Processing) ★ Plan design architecture. ★ Develop high quality digital design. ★ Be familiar with IC design flow. [Minimum Qualifications] ★ Outstanding problem analysis and debugging skills. ★ Experienced in C language. ★ Experienced in Verilog RTL language ★ Experienced in digital IC design front-end flow ★ Experienced in CAD tool usage such as simulation tool, linting tool, synthesis tool, member compiler [Preferred Qualifications] ★ Nice to have experiences in scripting language. ★ Nice to have experiences in FPGA flow

1. 具 0~2年數位晶片設計，或有 0~5年類比晶片設計工作經驗。 2. 具備基本數位和類比電路知識，熟習標準晶片設計流程。 3. 熟習業界常用EDA tools, 或Matlab/ Simulink。 4. 研習過CMOS or BiCMOS 類比設計電路課程，對放大器有基礎認識。 5. Experience in these areas is preferred： * BiCMOS or CMOS high-speed (>20Gb/s) circuit, Linear electrical amplifier & equalizer, High-speed (>25G) CDR/PLL/SerDes. * Linear optical laser driver & receiver (TIA + linear amplifier) 本職位負責類比IC電路的設計、驗證和除錯。這是一個高度技術性的職位，對公司的產品開發至關重要。我們正在尋找一位熱愛類比IC設計並具有相關經驗的人才，以推動公司的技術創新和發展。 如果您對這個職位感興趣，請投遞您的履歷表，我們立即與您聯繫。