「Signal Integrity Engineer(TDC)」的相似工作

THE ROLE The Lead Signal Integrity Engineer is a technical leader responsible for advancing Isola’s laminate materials to meet and exceed high-speed electrical and signal integrity (SI) performance requirements. This role provides mentorship and direction to the Signal Integrity team in Taiwan, drives innovation in SI test methodologies, and ensures strong technical engagement with global OEMs. The Lead serves as a recognized authority in SI, bridging customer needs with material performance and representing Isola in the high-performance electronics community. KEY RESPONSIBILITIES: Customer-Facing Technical Support: • Lead technical engagement with OEMs and direct customers on high-speed laminate characterization. • Act as primary technical contact for SI-related design validation and adoption cycles. • Oversee the creation of technical reports, white papers, and collateral for internal and external use. Strategic & Technical Leadership: • Define and develop advanced SI measurement, modeling, and simulation methodologies. • Collaborate with Product Management, R&D, and Sales to ensure alignment of SI capabilities with product strategy. • Represent Isola as a thought leader through publications, conferences, and industry forums. Organizational Management: • Mentor, guide, and grow the Taiwan-based Signal Integrity Engineering team. • Establish scalable, cost-effective SI test methods that accelerate R&D and customer response. • Drive alignment with global Application Engineering teams to ensure best-in-class technical service. Technology & Standards Thought Leadership: • Maintain expertise in SI methods, PCB processing effects, and high-speed digital design requirements. • Contribute to industry standards development and support customer forums on SI requirements. QUALIFICATIONS & EXPERIENCE • 8+ years of experience in signal integrity engineering, PCB laminates, or high-speed design. • Expertise in VNA measurements, probing techniques, and advanced SI methodologies. • Experience with PCB manufacturing and processing effects on SI performance. • Demonstrated leadership and mentoring experience. • Proven record of technical publications, white papers, or conference presentations. EDUCATION • PhD or Master’s in Electrical Engineering or related field required. OTHER CONSIDERATIONS • Fluent in English – required for global communication and technical documentation. • Proficiency in Mandarin Chinese – strongly preferred for engagement with Taiwan/China teams and customers. • Ability to travel regionally and globally as needed.

工作內容 1. 負責Ansys SIwave/HFSS/Q3D 等高頻軟體技術支援，包含售前/售後支援、教育訓練 2. 拜訪客戶介紹、推廣軟體以及解決方案 3. 與原廠技術團隊對接，協助溝通/解決客戶問題、學習軟體新功能 4. 高頻相關工程專案規劃與執行 5. 支援公司市場行銷活動 ---------------------------------------------------- 本公司具備Ansys產品專業技術人員，擁有廣大的技術資源供學習， 市場遍及台灣、中國及東協等地。 我們不斷地開拓新技術及市場，誠摯希望有志一同的你加入~ 歡迎光學、電磁學、電子電路、電磁干擾、光波導、矽光子各領域專家加入我們的團隊!! 思渤科技培養的不只只針對工作需求的專業工程技術人才， 更是培養技術人才自身技術品牌的職涯延伸， 讓你不單只是單一技術在此發展， 而是廣闊長遠的打造出個人技術品牌知名度， 讓你在專業領域中與更多佼佼者一起發光發亮!! ｜遠距辦公。節省通勤成本。溝通不斷線｜ ☆業務試用期三個月通過後，即可申請遠距辦公方式！ ☆每週只需進公司辦公一天，剩下四天靈活運用外勤出差或在家辦公，節省塞車通勤時間，線上溝通快速不斷線。 ｜舒適好開公務車。公務拜訪便利又安全｜ ☆提供三年內新車預約公務拜訪使用，安全又舒適。 ☆不需自己養車，找車位，公司定期保養管理，外勤無負擔。 ｜薪獎優渥。輕鬆get百萬年薪！｜ ☆業績獎金 ☆盈餘獎金 ☆年終獎金 ☆中秋、端午獎金 ☆配發公務機 ☆結婚禮金/生育津貼 ☆推薦人才獎金 ☆近3年平均調薪幅度3~5%

1.連接器、測試板高頻產品訊號量測 2.分析SI訊號完整性與提升改善 3.具連接器相關經驗者佳

a. SI訊號/PI電源完整性模擬分析 (Pre-Layout & Post-Layout) b. PCB/Layout設計建議與Guideline制定 c. SI/PI/EMI新技術專研與導入

1. 針對高速介面進行信號完整性模擬。 SI simulation : TDR, S parameter,Eye diagram,Crosstalk.. 2. 電路板電源完整性模擬。 PI simulation : IR Drop , PDN.. 3. 對於佈局圖給予改良建議。 Polar應用及評估PCB & VNA材料選擇方式 4. 信號完整性異常除錯。

【產品範疇】 1.DDI / TP / TDDI/ TCON/ Power等顯示相關產品 【工作內容】 1. SI/PI/EM issue solving, performance optimization, and design rule development 2. Chip/PKG/Board simulation and measurement for SI/PI/EM issue. 3. Co-work with system engineers, IC designers, and customers on product design-in tasks.

1.SI/PI量測與模分析 2.網路分析儀與探針平台操作 3.量測與模擬數彙整 4.機台操作：網路分析儀 5.專業知識需求：電磁學、微波工程、SI/PI理論分析

1. RF天線最佳化模擬。 2. 電磁元件設計模擬。 3. 相關量測(RF天線)。 4. 能獨立工作及專案執行。

1. 硬體電路設計與開發 • 根據專案需求進行系統架構規劃與電路設計（數位、類比、高速訊號） • 繪製原理圖（Schematic）與零件選型 • 與 PCB Layout 工程師合作進行電路板設計與佈線優化 • 評估並引入新技術與元件（CPU、GPU、DDR、Type-C、PD 等） 2. 功能實現與原型驗證 • 製作與驗證原型機（Prototype / EVT） • 分析與解決電路功能異常、訊號完整性（SI）及電源完整性（PI）問題 • 測試高速介面（USB, PCIe, HDMI, DP, Thunderbolt）與相容性驗證 • 優化功耗與散熱設計 3. 測試與驗證 • 制定並執行硬體測試計畫（功能測試、效能測試、穩定性測試） • 協助進行安規（EMI/EMC）、安規認證（UL、CE、FCC 等） • 進行系統相容性測試（各型周邊裝置、作業系統） • 與測試團隊合作分析並修正問題 4. 跨部門專案協作 • 與機構工程師（ME）協調 PCB 尺寸、元件擺放與散熱方案 • 與軟體工程師（SW）共同除錯（Debug）與韌體開發支援 • 與專案經理（PM）對齊時程與需求 • 與供應商（ODM/OEM/零件廠）討論設計、良率與成本 5. 量產支援與問題解決 • 支援試產（PVT）與量產（MP）階段的硬體異常分析 • 協助改善製造良率與穩定性 • 處理現場生產問題（SMT、組裝、測試工站） 6. 文件與版本管理 • 編寫與維護設計文件（原理圖、BOM、設計規範） • 設計變更（ECO/ECN）與版本控制 • 測試報告與問題追蹤（Issue Tracking）

1.PCB stack-up design & Constraint Rule setting. 2.Provide SI/PI design suggestions for PCB layout. 3.Signal integrity analysis of high-speed and low-speed signal interfaces. 4.Power integrity design includes DC impedance, AC resonance and capacitance optimization. 5.In addition to Cadence 2.5D EM solution as a daily necessary software, AMD SeaSim/S2Eye, Intel ICAT/IMLC/CCT are also required. 6.Use TCL and Python to shorten the complicated software operation process, generate reports and perform DOE analysis. 7.Familiar with PCB test coupon TDR/TDT measurement and Delta L 4.0 Measurement.

1、 負責Ansys高頻電磁場模擬分析軟體之售前拜訪、資料蒐集 2、 技術支援以及技術文件製作;訓練教材製作以及教育訓練。 3、 軟體安裝、簡報製作 4、 Ansys高頻電磁場(SI/PI)模擬分析軟體產品功能研究 5、 高頻相關工程顧問服務專案執行與規劃 6、 高頻相關產業趨勢研究。

Purpose of this Position 深入研究高速訊號，在高速硬體電路Signal Integrity上提供最佳設計且確保生產品質 Major Areas of Responsibility 專案研發 - Perform high speed signal integrity simulation including 10G/40G、25G/100G、PCIE、SATA、DP、USB、DDR3/DDR4/DDR5. - Perform pre-layout, layout constraint, and post-layout simulation processes. - PCB stackup design and layout review for high speed signal and PDN. - Build component models to ensure the correlation between SI/PI simulation and measurement. - Solid SI experience in resolving technical issues and performing detailed analysis. 團隊合作 - Collaborating with EE teams to refine high-speed signal performance. - Collaborate with the layout engineer to provide clear layout guidelines and enhance footprint optimization.

PRIMARY JOB DESCRIPTION: • Responsible for performing signal integrity and power integrity simulation analyzing DIMM products in different form factors. • Work with layout team and NPI team for achieving good board routing and releasing to production • Will interface with SMART global design teams PRINCIPAL DUTIES AND RESPONSIBILITIES: • Perform channel margin analysis to provide design tradeoffs among package, board, and connector on products starting from the technical specifications from different controller and NAND flash vendors in different form factors • Perform PCB timing analysis, work with layout designers and hardware engineers to implement all signal integrity rules • Perform PCB power margin analysis, work with layout designers and hardware engineers to implement all power integrity rules • Develop layout signal/power integrity rules guideline or document on new products starting from the technical specifications from different DRAM vendors in different form factors • Capability to execute trouble shooting and provide workable solution to SMART global R&D teams and customers • Communicate and work closely with global R&D teams to achieve targeted schedule for PCB board release • Write a Layout guidance document. Organize and research technical reports and share

1. 馬達磁路設計 2. 電磁場模擬分析 3. 新技術研究與導入 4. 馬達性能測試與驗證工作 5. 馬達開發專案執行與管理 6. 供應商及產線溝通協調 7. 問題解析與處理

1.類比訊號分析及電路設計。 2.小信號低雜訊放大線路的設計、模擬、量測及驗證。 3.熟悉OPAMP, Filter, ADC/DAC,… 規格, 性能特性及應用。 4.電子電路硬體的設計、驗證，失效分析和故障排除 5.萬潤熱烈招募有意投入設備產業的菁英，如未具備本項職缺所需相關技能與工作資歷者 亦歡迎投遞，薪資另議。 6.上班地點 新竹：新竹市工業東四路24-2號2樓 /新竹縣竹北市保泰三路 78 號 台中：台中市西屯區工業區37路18號 高雄：高雄市路竹區路科十路1號

工作需求 (Job Requirements) 1.電子相關科系大學或碩士以上 2.2-5年的SI(訊號完整性)設計相關工作經驗 3.熟悉相關SI模擬軟體工具相關經驗 4.需與亞洲不同地區的辦公室協助合作 5.能獨立完成公司交辦的工作 工作職責 (Job Responsibilities) 1.負責3D高頻模擬軟體之售前拜訪、技術支持、產品培訓及專業規劃與執行。 2.熟悉PCB、SI信號完整性等相關模擬經驗 3.負責3D軟體的應用及技術支持給現有與新的潛力客戶 4.負責準時完成主管分配的工作

1. 熟悉電子電路設計，具原理圖繪製與PCB Layout協同經驗 2.能獨立規劃與設計 Router、Layer3 Switch、FWA CPE 等網通產品主板 3.了解常見電源架構設計（DC/DC、PoE、LDO 等） 4.具備 EMI/EMC、ESD 設計與除錯經驗 5.能協助產品從 EVB → EVT → DVT → PVT → MP 轉換流程 6. 負責產品驗證及除錯改進及量產可製造性評估 7. 產品維修SOP製作或生產標準的改良方案，以達到在設備性能限制下的最佳品質。 8. 協助驗證電子零件及產品BOM審核 9. 工作態度正向主動積極

如果你很懂： 1. Signal Integrity (信號完整性)分析/設計/測試，高頻測試版/測試系統設計與分析 2. CST 相關高頻模擬軟體 3. 高頻cable或零組件之訊號/雜訊設計/測試與debug 4. 會IEEE 802.3 系列或PCI-e規格 期待你可以： 1.跨部門溝通確認機構/客戶需求與高頻特性 2.針對連接器/線材高頻特性提出設計改善方向與模擬結果 3.協助分析PCB高頻特性與提出設計改善方案 4.能進行高頻分析,並建立模型讓模擬與實品盡可能趨近

1. Electromagnetic simulation and electrical modeling by using Ansys EM suite. 2. SI/PI high frequency / high speed signal integrity / power integrity / antenna radiation with Ansys EM/ADS systems. 3. 3D full wave FEM/FDTD large-scale simulation and validation with EMpro and HFSS HPC. 4. Signal emulation and performance simulation in PCB/Substrat of optical module.

About Ubiquiti At Ubiquiti Inc., we create technology platforms for Businesses, Smart Homes, and Internet Service Providers, driven by our goal to connect everyone, everywhere. To date, Ubiquiti has shipped over 100 million devices worldwide, from ISP networking products to the next generation of IT solutions. Our growth is made possible by the dedicated team of hundreds behind the scenes. From software developers and product managers to designers and strategists, Team UI is driven to achieve our common goal: Rethinking IT. At Ubiquiti, you’ll heighten your potential and broaden your horizons, all while shaping the future of connectivity. Responsibilities - Perform electrical validation of high-speed interfaces such as PCIe Gen3~Gen5, Ethernet (802.3 10G/25G/100G/400G), DDR4/5, SATA, and USB3 - Perform electrical validation of low-speed interface, including I2C, SPI, MDIO, eMMC, and RGMII. - Perform chip-to-chip SerDes signal validation, including SGMII+, UXSGMII interfaces. - Plan and execute power testing strategies for multiphase power stages and DC buck converters. - Perform power integrity validations, including ripple noise analysis, power sequencing verification, electronic load (E-load) operation, and power supply unit (PSU) evaluation. - Develop and execute test scripts under Linux environments, familiar with shell commands and automation scripting. - Collaborate with the HW team and chip vendor to define and document SI/PI validation plans and requirements. - Analyze and identify SI/PI issues, and work closely with HW, FW, layout teams, and chip vendors to develop improvement solutions that enhance electrical performance and signal integrity quality. Requirement - Solid experience with SI test equipment (oscilloscope, BERT, VNA, TDR). - 3+ years of hands-on experience in Signal Integrity, and SerDes/PCIe/USB/DDR validation. - Solid understanding of compliance testing methodologies, eye diagram, and litter analysis. - Strong understanding of low-speed interface protocols and comprehensive experience in AC/DC characteristic validation. - Bachelor’s/Master’s degree in Electrical Engineering, Electronics, or related fields. - Excellent problem-solving skills, ability to debug SI/PI issues, and strong cross-functional communication with HW design and layout teams. Preferred Qualifications - Experience working on system-level signal validation in server, networking, or storage platforms with high-speed interfaces. - Familiarity with Power Integrity validation, including power sequence, ripple noise, OCP, and SCP testing. Benefits - International work environment and collaboration with global development teams - Excellent work conditions - Competitive package: great pay, perks, and benefits - Group insurance and health coverage - Flexible working hours and patterns - Complimentary drinks and snacks at the office