負責 Display Port IP 規劃與設計
工作內容:
Display port IP leader
Display port IP architecture definition
RTL design and functional verification
FPGA verification
Synthesis and static timing analysis
1. Algorithm/Spec to RTL design, verification and synthesis
2. IP FPGA verification
3. Stardand IP configuration, integration and verification
4. Whole chip/Subsystem IP Integration and verification
1. Project integration support & implementation, to deliver qualified nestlist from RTL.
2. preSTA/SYN/LEC/postSTA/etc. EDA flow execution and enhancement
3. Timing & power closure
4. Schedule control, netlist optimization, flow coordinator
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[工作內容]
1. Responsible for design and development of digital ICs, including Verilog RTL coding, functional verification, and optimization.
2. Participate in the complete ASIC design flow: specification, RTL design, synthesis, static timing analysis, and physical design handoff.
3. Perform Design-for-Test (DFT) implementation, including scan insertion and MBIST, to support manufacturability and testability.
4. Support SoC integration, including bus protocols (AMBA) and high-speed interfaces (PCIe, SerDes).
Job Description: Are you ready to push the boundaries of what's possible in technology? Join the trailblazers at Sandisk. As a Principal Engineer you will be at the forefront of designing high-performance SoCs for storage solutions. By leveraging your expertise in RTL design and modern tools like GitHub Copilot, you will enhance the design process and productivity. You will collaborate with cross-functional teams to deliver groundbreaking solutions that meet our high standards of quality and performance.
Key Responsibilities:
• Innovate, implement, and verify RTL code for complex ASICs.
• Performed design tasks across various design stages.
• Utilize advanced AI-driven tools, including GitHub Copilot, to streamline the design process.
• Collaborate with hardware and software teams for seamless integration.
• Provide mentorship to junior engineers.
• Stay abreast of the latest industry trends and emerging technologies in AI and ASIC design.
Qualifications:
• Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field.
• Hands-on experience in digital IP/SoC design: minimum 7 years with a Bachelor's degree, or 6 years with a Master’s degree.
• Proven experience in ASIC RTL design, with a strong grasp of Verilog/System Verilog.
• Familiarity with the whole digital design flow.
• Proficiency in leveraging AI tools, including GitHub Copilot, for design and development.
• Strong problem-solving skills and the ability to thrive in a dynamic environment.
• Excellent communication and teamwork abilities.
Preferred Qualifications:
• Experience in low-power design techniques and methodologies.
• Familiarity with high-speed interfaces (e.g., SD Express, Compact Flash, PCIe, DDR).
• Proficiency in scripting languages (e.g., Python, TCL) for automation.
About Sandisk: Sandisk, a leader in data storage solutions, is seeking talented and experienced ASIC RTL Design Engineers to join our cutting-edge team. Our mission is to revolutionize the data storage industry through relentless innovation and technology breakthroughs.
1. Architecture design and RTL implementation of Automotive/Smartphone chipset
2. SoC system power and performance analysis
3. SoC system bus and memory subsystem design, integration, and modeling
4. SoC low power design, integration, and modeling
5. SoC functional safety analysis, design, integration, and modeling
6. SoC cyber security analysis, design, integration, and modeling