Hands-on experience in the design and development of at least one of the following analog circuits: ADC, DAC, PGA, high-speed analog driver, PLL, or SerDes.
Job desicription:
Our Design Team specializes in the challenging field of Non-Volatile Memory (NVM) IC circuit design. We are actively seeking an experienced Analog Circuit Design Engineer to contribute to our cutting-edge developments in embedded NVM solutions and surrounding circuitry.
As a key member of our team, you will be responsible for the design, verification, and debugging of essential analog building blocks like Bandgap references, LDOs, and Charge Pumps. A significant part of your role will involve designing critical memory peripheral circuits for NVM IP and test chips, including Array interfaces, Decoding logic, and Sense Amplifiers.
Your responsibilities will span the design lifecycle, from contributing to IP specifications and core circuit design to ensuring performance through layout optimization and comprehensive corner simulations of NVM IPs. We are looking for candidates with proven expertise in analog circuit design, ideally with prior experience in embedded memory or NVM technologies.
If you are an experienced analog designer eager to tackle complex challenges in non-volatile memory, we encourage you to apply and help shape the future of memory technology.
Job description
Join our innovative team specializing in cutting-edge embedded memory solutions. We are seeking Analog Circuit Engineers to play a key role in the design and development of high-performance embedded DRAM and associated peripheral circuits.
In this position, you will be responsible for the complete cycle of DRAM circuit design and simulation verification. Your tasks will involve developing novel circuit topologies, transistor-level design, optimizing performance metrics, and ensuring robust functionality through extensive simulations using industry-standard EDA tools.
Required qualifications include a strong technical background in Electrical Engineering, Electronics Engineering, Computer Engineering, Physics, or a closely related field. Candidates must possess demonstrated, significant experience in DRAM circuit design and comprehensive simulation verification methodologies.
Ideally, candidates will have proven design experience in specific DRAM-related circuit blocks, including but not limited to:
Row and Column Decoder circuits
Control path logic
DC-DC converters, Charge Pumps, and Bandgap References
Delay Locked Loops (DLLs) and Phase Locked Loops (PLLs)
Negative voltage generators (NVG) and other critical peripheral circuits
This is an excellent opportunity to contribute to state-of-the-art embedded memory designs in a dynamic, collaborative environment. If you are a skilled analog designer passionate about solving complex challenges in DRAM circuitry, we encourage you to apply and help shape the future of embedded memory technology.
1、Mixed signal IC design and verification
2、Familiar with analog circuit designs including OPAMP/PGA, Analog active filter, ADC, DAC, level shifter, CDR, charge pump, PLL, bandgap reference
3、Co-work with board-level designers to analyze power and signal integrity of PCB.
4、Transmit signal & Noise characterization and analysis
5、Experience Preferred:
3-year work experience in the following fields
High-speed serdes TX/RX application
Pipeline ADC / SAR ADC
6.、Master or Ph.D. degree in EE
1.Design and maintain analog circuits
2.Survey and maintain design processes
3.Survey and maintain design tools and flow
4.Help training junior engineers
5.Debugging and measuring chip
We are looking for a proactive and challenge-driven engineer to join our memory design team. This role primarily focuses on gate-level simulation and functional verification to ensure product quality and alignment with specifications.
【Key Responsibilities】
1. Memory circuit design and verification.
2. Gate-level verilog simulation against to the datasheet.
3. Failure mode analysis.
【Qualifications】
1. Experience in SRAM, DRAM, or other memory product design.
2. Solid understanding of digital circuit design and Verilog HDL.
3. Experience with simulation and debugging, able to work independently.
4. Hands-on experience in failure mode analysis is a plus.
5. Deep RTL design experience is not required, but strong gate-level simulation and verification skills are essential.