「類比IC設計資深工程師_LDO」的相似工作

【產品線描述】 1. LCD Power IC 2. 手機及穿載 Power IC 3. USB Type C Power delivery (MCU開發驗證經驗，相容性驗證) 【工作說明】 1. 面板及手機應用的電源管理, 背光驅動晶片開發 2. 需求條件: 2-1. 可獨立完成Buck, Boost, Buck-Boost 等DC/DC電路設計 2-2. 可獨立完成Charge Pump, LDO, OP等類比電路設計 2-3. 熟悉Battery Charger, Battery Protector尤佳 2-4. 熟悉ADC(Sigma-Delta, SAR), PLL尤佳 【共創A+聯詠】 穩健踏實、專家精神、創造優勢 驅動科技、開發創新、引領未來 邀請優秀人才，共創A+聯詠

記憶體power system 設計 『具工作經驗者，薪資另議』

Analog IC design (A) Power Management(SMPS, Buck, Boost, LDO, Battery Charger)， (B) Analog Circuit Design

【產品線描述】 高速傳輸 (USB4.0、DisplayPort、PCIe) 電路設計 (High Speed Serdes, Rx/Tx/Clocking, CTLE, DFE, CDR, PLL) 【工作說明】 高速介面、混合訊號類比電路設計 工作內容包含下列項目: 1. CDR architecture design (1/N-rate, DLL-based, PLL-based, PI-based)、DeMux 2. Adaptive CTLE/DFE 3. High speed ADC / Time-Interleaved ADC design 4. RF circuit related / EM related 5. PLL circuit/architecture design 6. High speed transmitter with FFE、P2S 7. High performance oscillator design (Ring/LC) 8. Impedance matching design 9. Circuit calibration techniques & flow 10. SerDes system behavior modeling & analysis 11. Chip Integration & Verification 【必要條件】 1. Master of Science / Above degree in Electrical Engineering, strong mixed-signal design concept. 2. 2-years above experience. 3. Familiar with design and simulation tools (Cadence's design environment, Circuit simulation : Spectre, HSpice, Finesim). 4. Strong debugging and analytical skills. 5. Clear communication skills and team work ability are necessary. 備註：上班地點為「台北」或「竹北」或「竹科」

我們專注於能源晶片與深度演算法的融合創新，誠徵類比IC演算法工程師，將傳統的手工類比設計流程轉化為自動化的智慧演算法，讓電路設計更高效、更穩定，推動類比設計的未來。 你將負責： 開發電路拓撲分析演算法 設計 sizing 最佳化演算法（基於 gm/Id methodology 等） 將手工設計流程轉化為程式化流程 協助建立類比IC設計自動化工具 與軟體團隊合作進行演算法驗證與優化 熟練使用 Vibe Coding 工具（Cursor、Github Copilot、Claude… 等）更佳 我們期待你具備： 類比IC設計實務經驗 熟悉運算放大器、ADC/DAC、電源管理電路等拓撲設計 精通 SPICE 模擬與電路參數萃取 深度理解 sizing methodology（如 gm/Id 設計法） 能清楚闡述設計 trade-off 與電路原理 加分條件： 具備 Python 程式能力 有將手工設計方法轉換為程式實現的經驗 具備統計分析能力（Monte Carlo / corner analysis） 有 EDA 工具 API 開發經驗 熟悉圖論演算法與資料結構 如果你熱愛把設計方法變成程式，並用演算法重新定義類比IC設計的可能性，歡迎加入我們！

Digital IC design engineer - Familiar with Verilog RTL coding - Familiar with digital design flow (pre-layout simulation, timing constraint, synthesis, post-layout simulation) - Will be working on high speed Serdes IPs - Experience or interest in all-digital PLLs or clock-data recovery circuits is a big plus

1. SAR ADC / Current steering DAC/ SDM ADC/ DAC related 2. Analog Baseband related 3. 據有類比整合相關經驗佳

Job description Join our innovative team specializing in cutting-edge embedded memory solutions. We are seeking Analog Circuit Engineers to play a key role in the design and development of high-performance embedded DRAM and associated peripheral circuits. In this position, you will be responsible for the complete cycle of DRAM circuit design and simulation verification. Your tasks will involve developing novel circuit topologies, transistor-level design, optimizing performance metrics, and ensuring robust functionality through extensive simulations using industry-standard EDA tools. Required qualifications include a strong technical background in Electrical Engineering, Electronics Engineering, Computer Engineering, Physics, or a closely related field. Candidates must possess demonstrated, significant experience in DRAM circuit design and comprehensive simulation verification methodologies. Ideally, candidates will have proven design experience in specific DRAM-related circuit blocks, including but not limited to: Row and Column Decoder circuits Control path logic DC-DC converters, Charge Pumps, and Bandgap References Delay Locked Loops (DLLs) and Phase Locked Loops (PLLs) Negative voltage generators (NVG) and other critical peripheral circuits This is an excellent opportunity to contribute to state-of-the-art embedded memory designs in a dynamic, collaborative environment. If you are a skilled analog designer passionate about solving complex challenges in DRAM circuitry, we encourage you to apply and help shape the future of embedded memory technology.

We are seeking a skilled Analog IC Design Engineer with expertise in MIPI TX/ PLL design and sensor readout circuits. The ideal candidate will possess a strong foundation in analog design and a passion for developing cutting-edge solutions in a collaborative environment. 1.Design and implement MIPI TX and PLL circuits for high-speed data transmission. 2.Develop charge pump and LDO (Low Dropout Regulator) circuits to ensure efficient power management. 3.Design and optimize oscillator (OSC) circuits for precise timing applications. 4.Create sensor readout circuits, including CDS (Correlated Double Sampling), TDC (Time-to-Digital Converter), ramp circuits, DAC (Digital-to-Analog Converter), and comparators. 5.Collaborate with system engineers to define specifications and ensure alignment with overall project requirements. 6.Perform circuit simulations and analyses using tools such as Cadence, Spectre, or HSPICE. 7.Conduct design verification and validation through prototyping and testing. 8.Optimize designs for performance, power efficiency, and reliability. 9.Participate in design reviews and contribute to project documentation. 10.Provide support during the layout and fabrication process. Preferred Qualifications: 1.Familiarity with IP design principles. 2.Experience with mixed-signal circuits. 3.Knowledge of low-noise and high-speed design techniques.

We are currently seeking a talented Analog Design Engineer to join our team and participate in the development of Power IC for High-Performance Computing (HPC). The role will primarily involve working on the design and development of the following components: 1. PMIC (Power Management Integrated Circuit) 2. Multiphase VR (Voltage Regulator) 3. Buck/Boost/Buck-Boost Converters 4. eFuse (Electronic Fuse)

1. 顯示驅動IC 類比電路設計 2. 電源管理IC 類比電路設計 3. 高速介面 類比電路設計 4. 觸控類比前端感測類比電路設計

1. Main responsibility is to design analog IPs in MCU such as adc/dac, pll, osc, por, ldo 2. 具備DC-DC Converter, Buck相關電路設計 2. Responsible for analog IP design, verification plan, test plan, document 3. Communicate with system, layout and digital engineer to ensure high quality --------------------------------------------------------------------------------------- 雅特力科技創立於2016年，為智原科技子公司。 【Artery雅特力】即將在台上市的IC設計公司，主要產品為32bit ARM core base MCU 公司網址：https://www.arterychip.com 關於雅特力：https://www.104.com.tw/company/1a2x6blojm

Responsible for developing custom IP for SoC design from specification definition, circuit design to testing, and familiar with component and process characteristics.

1. 16bit ADC/DAC design experience 2. PLL/DLL/RF/OSC/POR/LVDS design experience 3. LDO/DC-DC design experience 4.Guide layout engineer to make a compact & working layout

1. 專案開發前期: 協同SA訂定規格/設計環境建構/競品特性分析/協同PM訂定開發時程表 2. 專案開發期間: 支援電路設計及整合/定期招開設計檢查會議/定期追蹤開發進度/確保專案各站點完成時程/準備各站點檢查資料及文件/測試相關資料的準備 3. 專案開發後期: 分析CP驗證數據/確保良率達標/協同SA,RD,TE進行除錯分析/確保達送樣標準

1. 觸控IC、TDDI或指紋辨識 IC 開發經驗 2. ADC或sensor IP 開發經驗 3. TFT-LCD或OLED Display driver IC 開發經驗 4. Charge pump、LDO、Source driver、Gate driver、High speed interface、OSC、BGR 相關開發經驗 5. 工作地點：【台南、新竹、台北】 以上其中任何一項相關者佳。

5G手機,AR,VR 顯示技術,AI 人機介面的3D觸控顯示技術,整合生物特徵的全面屏顯示技術。 【工作說明】 1. 高速介面的電路評估,規劃,設計與驗證. 2. 低功耗,高速的SRAM電路評估,規劃,設計與驗證. 3. 高精度,低溫漂的時脈電路評估規劃,設計與驗證. 4. 低功耗,快速嚮應的regulator 電路評估,規劃,設計與驗證. 5. 非揮發性記憶體電路評估,規劃,設計與驗證. 6. 高效率 DC/DC circuit design評估,規劃,設計與驗證. 7. 低功耗,低偏移的OPAMP電路評估,規劃,設計與驗證. 8. 低雜訊的DAC/ADC電路評估,規劃,設計與驗證. 【必要條件】 研究所以上相關科系畢業 熟悉類比電路設計,混合信號處理, 對類比電路設計充滿熱忱者

1.SERDES CMOS Circuit Design ( HDMI,DisplayPort, or USB3.0 ). 2.All Digital PLL Circuit Design.

1.類比訊號分析及電路設計。 2.小信號低雜訊放大線路的設計、模擬、量測及驗證。 3.熟悉OPAMP, Filter, ADC/DAC,… 規格, 性能特性及應用。 4.電子電路硬體的設計、驗證，失效分析和故障排除 5.萬潤熱烈招募有意投入設備產業的菁英，如未具備本項職缺所需相關技能與工作資歷者 亦歡迎投遞，薪資另議。 6.上班地點 新竹：新竹市工業東四路24-2號2樓 /新竹縣竹北市保泰三路 78 號 台中：台中市西屯區工業區37路18號 高雄：高雄市路竹區路科十路1號

歡迎2026年畢業並正在找尋研發替代役的同學申請! 職位選擇: Direction 1: Mixed Signal Design Engineer Direction 2: Mixed Signal Analog Circuit Designer What you’ll be doing: • Develop and implement high speed interfaces and analog circuits. You will have hands on experience taking innovative integrated circuit designs at data rates of 25Gbps and higher from concept through silicon characterization. • Help by defining circuit requirements and complete design from schematic, layout, and verification to characterization. • Conduct schematic design of deep-submicron CMOS technologies using Spectre, Hspice or like. • Take ownership for the architecture, transistor design and verification using industry standard EDA tools such as Cadence virtuoso. • Optimize circuit to meet the specifications for system performance. • Work closely with layout engineers by providing detailed floorplan and guidance for matching and high-speed routings. • Provide support for post-silicon bring-up and debugging. What we need to see: • Hold a Master of Science/Ph.D in Electrical Engineering, Computer Engineering or related field with strong analog design background • CMOS Analog / Mixed Signal Circuit Design Experience in deep sub-micron process (especially in FINFET) • Experience with design and verification tools (Cadence's IC design environment, analog circuit simulation tools like Spectre, HSpice, Finesim, XA) • Experience in crafting test bench environments for component and top level circuit verification • Behavioral modeling of analog and digital circuits • Strong debugging and analytical skills • Analog simulation for noise analysis, loop stability analysis, ac/dc/tran analysis, monte-carlo, etc. • Strong interpersonal skills and ability & desire to work as a great teammate are huge plus. 應徵方式: 請提供以下資料： • 英文個人履歷 • 學士+碩士成績單 (中英文皆可) 提交申請: 請將上述資料投遞至104，符合資格者將會收到進一步的聯繫通知。