「EDA應用工程師_Application engineer」的相似工作

Please apply this role through https://careers.synopsys.com/job/hsinchu/r-and-d-engineering-sr-staff-engineer/44408/84900058096 Synopsys is looking for motivated Product Engineer to help design, develop and test state of the art Static Timing, Characterization and Library modelling tools. The primary focus of the Product Engineer is closely working with R&D team, to influence technologies/solution roadmaps and provide R&D team with accurate input from Field AEs, helping them focus on the most critical design challenges and help define solutions to critical problems. The engineer will work closely with Field AEs, ensuring overall consistency of end-to-end design and analysis flow to meet customer needs. The engineer will also work with Sales and Marketing teams to find and develop new markets, drive new tool evaluations and help customers with the adoption and continuous usage of Static Timing, Characterization and Library Modelling, thus enabling Chip Design customers achieve best Timing, Power and Characterization Goals. Synopsys’ existing and forthcoming tools offer an advanced transistor-level static timing characterization and library modelling solution that addresses the existing and emerging challenges in custom and memory design. They offer predictability and improved productivity to designers. Their concurrent timing, SI features and advanced variation aware analysis enables designers to accurately and quickly identify design issues early-on and avoid expensive late-finding of problems in silicon. Main responsibilities: • Drive new products and new product features that exceed customer needs. • Work with RnD to enable timely implementation of new products and features, and important bug fixes. • Provide consultation to prospective users and/or product capability assessment and validation. • Provide tool trainings to customers and Field AEs. • Provides technical expertise to sales staff through sales presentations and product demonstrations. • Assists the sales staff in assessing potential application of company products to meet customer needs and preparing detailed product specifications for the development and implementation of customer applications/solutions. Requirements: We are looking for an innovative, motivated, and dependable person, with at least BS degree and 8+ years of recent hands-on experience including: · Exceptional expertise in transistor-level analysis and debug circuit level issues for SRAM, RF, ROM memories and Standard Cells. · Good exposure to static timing concepts and CMOS engineering fundamentals. · Good knowledge of TCL and or other scripting languages. · Very good communication, social and leadership skills. Plus: · NanoTime or PrimeLib experience highly desirable.

請務必投遞官網(12438): https://careers.synopsys.com/job/hsinchu/applications-engineering-staff-engineer-ic-validator/44408/84710683632 You Are: You are an innovative and resourceful engineer with a deep curiosity for solving complex technical challenges at the intersection of hardware and software. With a strong foundation in Electronic Engineering, Computer Science, or a related field, you are adept at leveraging your programming expertise—whether in Python, Tcl, Perl, or similar languages—to streamline and enhance engineering workflows. Your experience within UNIX/Linux environments equips you to navigate high-performance computing scenarios with ease. You thrive in collaborative, cross-functional teams and are energized by the opportunity to work closely with top-tier foundry partners and leading fabless companies. Your keen understanding of physical verification flows—such as DRC, LVS, PERC, FILL, and DFM—sets you apart, and you are eager to deepen your expertise in SoC physical design enablement, process effect analysis, and signoff. You are detail-oriented, capable of producing clear technical documentation, and communicate with clarity and empathy across diverse audiences. What You’ll Be Doing: 1.Delivering advanced physical verification solutions (DRC/LVS/PERC/Fill) for top-tier foundries and key fabless customers, ensuring high-quality silicon signoff. 2.Developing and validating process design kits (PDKs) and verification methodologies in collaboration with R&D and customer teams. 3.Partnering with R&D to innovate and improve Synopsys tools and flows, contributing to the evolution of physical verification technologies. 4.Providing hands-on customer support, troubleshooting issues, and delivering timely resolutions that enhance customer satisfaction and product adoption. 5.Coordinating with internal teams, including product managers and end-users, to align on best practices and ensure seamless integration of new technologies. 6.Documenting technical solutions, validation methods, and customer workflows for knowledge sharing and process improvement. 7.Staying up to date on industry trends and applying new insights to continuously optimize verification processes and tools. The Impact You Will Have: Accelerate the adoption and success of Synopsys physical verification products in leading-edge semiconductor manufacturing processes. Drive the development of robust PDKs and methodologies that enable customers to achieve first-time-right silicon. Enhance the quality and reliability of Synopsys verification tools through direct feedback and collaborative innovation with R&D teams. Strengthen Synopsys’ reputation as a trusted partner to top-tier foundries and fabless customers worldwide. Facilitate faster product cycles and reduced time-to-market for customers by delivering efficient and effective signoff solutions. What You’ll Need: BS or MS degree in Electronic Engineering, Computer Science, or a related field. Proficiency in at least one programming language, such as Python, Tcl, or Perl. Hands-on experience with UNIX/Linux environments and command-line tools. Familiarity with physical verification flows (DRC, LVS, PERC, FILL, DFM) and understanding of complex layout/electrical design rules. Strong investigative, analytical, and problem-solving abilities, with a passion for learning new technologies. Ability to produce clear, concise technical documentation and validation reports. Prior knowledge of tool/runset development/support and experience with SoC physical design is a plus.

1. 管理及維護Linux系統工作站。 2. 管理及維護EDA Tools。 3. IC設計流程開發、驗證及維護。

1. Front-end IC design flow development/maintain/support 2. Experience in front-end design flow and familiarity with Prime Time,Prime Closure,Fusion Compiler. 3.Good understanding of timing sign off,constraint and timing closure methodology.

【產品範疇】 Mobile/TCON - LCD display driver、OLED display driver Tablet - LCD display driver TV/NB -LCD display driver TCON 產品 【工作內容】 1.DRC/LVS Command file 撰寫&Maintain 2.Laker TF/UDD/PCELL 撰寫 3.PERC rule & 程式的開發 4.Analog design flow development 5.Shell/SKILL/TCL/Python 程式開發 6.新製程廠內的PDK development 7.In house Utility 開發 8.AI 輔助工具的開發與評估

Job Contents · 3+ years of EDA flow expertise. · Responsible for timing closure / signoff flow development including timing closure methodology development, flow automation. .SDC validation , domain knowledge enhancement · Project support/execution & collaboration with EDA vendors. · STA sign-off flow/scripts/environment development for advanced process nodes.

招募導入水處理設備流程中計劃和設計階段裡使用CAD的工程師。 【工作內容】 ■ 接單前的計劃工作 ・應對客戶詢價與會議、系統研究、物料計算、成本計算、流程圖、配置設計、說明書製作、各種文件製作等。 ・優先考慮有志於將來向客戶提案最適合的系統和服務，並引領接單活動的過程工程師。 ・使用Inventor進行設備及設施的設計開發、導入及運營。 ・AutoCAD、Revit等軟體的操作。 ・進行Inventor操作及教育等相關工作。 ・經驗涵蓋流程圖、配置設計、說明製作、管道設計、採購設計、塔槽和機架設計、現場施工問題應對等，未來有機會成為專案設計leader！ 【魅力】 ・AI產業等蓬勃發展，目前半導體需求上升，業績穩定。 ・可以掌握日本半導體相關技術。 【法定項目】 ・勞健保 ・加班費 ・各種休假（特別休假、婚假、喪假、生理假、產檢假、陪產假、產假、育嬰假） ・退休金 【公司福利】 ・餐費津貼 ・員工旅遊（例：泰國） ・升遷制度 ・獎金（一年1次，平均2～3個月左右） ・出差津貼 ・員工聚餐

我們正在尋找一位熱情、有經驗的EDA應用工程師，加入我們充滿創新和技術挑戰的團隊。這位工程師將與台灣地區的客戶及合作夥伴緊密合作，提供最新的電子設計自動化工具和技術支援，以實現客戶的設計最佳化及效率提升。 職責： 與客戶端的工程師密切合作，了解其設計需求，提供EDA工具相關的技術支援。 協助客戶優化和自動化設計流程，以提高生產力和效率。 在EDA工具中執行模擬和分析，確保客戶設計的性能、功耗和可靠性符合要求。 解決客戶在設計過程中遇到的技術挑戰，提供解決方案以滿足其產品開發目標。 資格要求： 學士或以上學歷，專業領域包括電子工程、計算機工程或相關領域。 具備良好的問題解決和溝通能力，能夠有效協作並在客戶團隊中發揮領導力。 對IC設計、半導體及EDA產業有濃厚興趣，並追求不斷學習和專業成長。 必要條件： 具有相關EDA工具（如Cadence、Synopsys、Mentor Graphics等）的使用經驗。 熟悉硬體描述語言（SystemVerilog、Verilog、VHDL）和模擬工具。 英文聽說讀寫中等以上

(1)Must have BS in CS/EE of relevant experience in IC design field. (2)Familiar with IC design flow, placement and route (P&R), and layout. (3)Circuit knowledge and logic design relevant experience would be a plus.

[駐點於知名科技公司服務] 希望你對最新科技技術和EDA工具有強烈的學習熱情，並且願意參與從SYN、APR、signoff到Foundation IP最新技術的開發，將這些技術應用到最前沿的產品中。 1. 設計流程維護： 維護和優化CAD參考流程，助力IC設計。 確保設計流程性能和準確性達到最佳狀態，產出更優質的成果。 2. 工具整合： 整合各種EDA工具（如Synopsys、Cadence、Mentor Graphics）到參考設計流程中。 確保不同工具之間的相容性和無縫操作，提升工作效率。 3. 文件編寫: 創建和維護參考流程的全面文件。 詳細記錄所有更改和更新，方便用戶未來參考。 4. 性能監控： 監控參考流程的性能，識別改進區域。 實施增強措施，提高流程效率，縮短設計週期時間。

Position Description: 1. To provide key technical support in digital IC design implementation, product demonstration, and sales presentations. 2. To demonstrate strong ability and to be hands-on in RTL-to-GDSII design methodology, including both challenging low power and high-performance designs. 3. Have real design experience including floorplan and partition, place, CTS, route, STA timing closure, Physical verification, RC extraction, Power Network analysis. 4. Assist in technical evaluation, assessment and delivery of concurrent ASIC/SoC designs. 5. To play a leading role among other team members, while receive little instruction on routine and general assignments. Position Requirements: 1. A bachelor's degree is essential and 3+ years’ experience in IC design, electronic engineering or computer science applications. 2. Ability to understand and articulate technical issues, (and knowledge of) design products and their applications. 3. Requires working knowledge of one or more programming languages, and effective communication and soft skills. 4. An MS degree and/or working experience in multi-nation IC design house/or familiar with EDI/Innovus product is a plus. 5. Good communication in English and good work attitude. 6. Be familiar with shell/Perl/Tcl etc. script language.

Job Description We are seeking a talented individual who will participate Virtuoso PDK (Process Design Kit ) development, quality and PDK applications related projects with leading foundry. This position will support Virtuoso PDK quality delivery, SKILL programming in task delivery, also provide PDK applications related support and interact with customers to overcome challenge in a fact-pace environment. Position Requirements: • MS degree in Electrical Engineering, Computer Engineering or similar areas. • Experience in analog design flow support or PDK delivery. • Knowledge and experience with analog design layout/simulation/digital/analog IC design flow, with layout domain knowledge would be a plus. • Experience in Linux shell environment and script programming, such as Perl and Tcl preferred. • Good communication skills in English. • Desire to learn, to take the challenge and to be a team player.

擔任CAD (Physical Verification Design) 工作內容: •Development and maintenance of Calibre DRC/LVS/PERC/PM/xRC/xACT/3DSTACK. •Development and maintenance of ICV DRC/StarRC. •Physical verification flow design methodology. •Tapeout (PG) sign-off review.

At cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. You’ll develop state-of-the-art library characterization tools for our worldwide customers in an exciting and innovative environment. Position Responsibilities:  Full time in industry leading software development  Involvement in local customer engagements in cooperation with global teams  Develop new product features, including invention, design and implementation new algorithms to build industry leading products Desired Qualifications:  Experiences in EDA/IC industry  Experiences in library characterization, spice simulation, or transistor level timing  Effective communication skills, passion to drive a project and to win customers Additional Job Description  Experience in developing library characterization or circuit simulation software  High level understanding of SPICE simulation transistor models  Experience with distributed programming, database design, and cloud APIs for distributed computing  Proficiency designing data structures, algorithms, and software engineering principles  Experience in developing Machine Learning technology and deploy it at customers

Job Description: This position is in Cadence Pegasus Physical Verification R&D team in Hsinchu, Taiwan. The candidate for this position will be developing design rule check (DRC) and FILL decks for advanced nodes of semiconductor manufacturing, The job involves creating quality check (QC) patterns, writing physical verification DRC and FILL rules and developing decks consisting of these rules. It also involves testing these decks on real customer designs and troubleshooting the deck and tool issues, providing feedback to Pegasus Foundry Team, Pegasus R&D, and foundry partners. Requirement: At least 2 years of previous experience with DRC or FILL deck development, and BS or MS degree in engineering.

The VLSI Physical Design Engineer is responsible for implementing and optimizing the layout of integrated circuits (ICs) from netlist to GDSII. This role plays a key part in turning high-level logic designs into manufacturable silicon chips, ensuring electrical performance, area, and power (PPA) goals are met, and the physical verification results are good. Key responsibilities: 1. Derive full-chip and block-level physical design from netlist to tape-out (netilst to GDSII). 2. Floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and layout verifications. 3. Work closely with front-end design, DFT, and package teams to ensure design closure. 4. Sign-off on signal integrity, power integrity, reliability and manufacturability including performing static timing analysis (STA), IR drop analysis, EM analysis, and physical verification (DRC/LVS/DFM). 5. Analyze, optimize and resolve congestion, timing, power integrity and signal integrity issues. 6. Create and maintain physical design automation Tcl scripts, and flows development for design implementation. 7. Interface with EDA tool vendors and foundries to ensure design compliance and manufacturability.

投遞網址: https://careers.synopsys.com/job/hsinchu/r-and-d-engineering-sr-engineer/44408/85652406272 You Are: You are an experienced and passionate engineer with a profound curiosity for technology and a strong drive to solve complex problems. With a background in Electrical Engineering, Computer Science, Mathematics, or Physics, you have spent at least a decade mastering your craft, specializing in the intersection of software development and circuit design. Your expertise in C++/C programming, combined with a deep understanding of data structures, algorithms, and circuit simulation, sets you apart as a technical leader. You are comfortable navigating both analog and digital domains, leveraging your circuit design knowledge to drive innovation in electronic design automation (EDA) solutions. What You’ll Be Doing: • Designing, developing, and optimizing SPICE circuit simulation engines to enhance performance and accuracy. • Collaborating with global R&D teams to implement new algorithms and features for circuit analysis and optimization. • Analyzing and resolving challenging functional and performance issues in circuit simulation software. • Providing expert customer support, addressing technical inquiries, and guiding users through complex simulation problems. • Interpreting customer requirements and translating them into technical solutions and product enhancements. • Preparing and delivering technical presentations and documentation to both internal stakeholders and external customers. • Staying current with emerging trends in EDA, circuit simulation, and semiconductor technology to inform product direction. The Impact You Will Have: • Drive continuous improvement in Synopsys’ circuit simulation tools, directly impacting the success of semiconductor innovations worldwide. • Enable customers to achieve faster, more accurate chip designs by delivering robust and reliable simulation solutions. • Enhance the scalability and usability of EDA products, supporting the design of next-generation electronics. • Foster strong customer relationships through exceptional technical support and solution delivery. • Contribute to a collaborative, high-performance R&D culture that values knowledge sharing and creative problem-solving. • Shape the roadmap of Synopsys’ industry-leading simulation technologies through your insights and expertise. What You’ll Need: • MS or PhD in Electrical Engineering, Computer Science, Mathematics, Physics, or a related field. • 10+ years of hands-on experience in software engineering or circuit design. • Strong proficiency in C++ and/or C, with a solid grasp of data structures and algorithms. • Deep understanding of analog and digital circuit design principles. • Proven ability to analyze and resolve complex software or hardware issues independently. • Excellent English communication skills, both written and verbal. Who You Are: • Analytical thinker with a systematic approach to troubleshooting and problem-solving. • Effective collaborator who thrives in diverse, multicultural teams. • Proactive communicator with strong presentation and interpersonal skills. • Adaptable and resilient in the face of technical challenges and evolving priorities. • Detail-oriented, with a passion for delivering high-quality, reliable solutions. • Customer-focused, with a commitment to understanding and meeting user needs. The Team You’ll Be A Part Of: You will join a dynamic and innovative R&D team dedicated to developing advanced SPICE circuit simulation software. Our team brings together experts in software engineering, circuit design, and EDA solutions, working collaboratively across continents to deliver cutting-edge products. We thrive on tackling complex engineering challenges and are committed to continuous learning, knowledge sharing, and supporting each other’s growth. Your contributions will directly influence the capabilities and success of Synopsys’ simulation tools, empowering customers around the world.

大塚是一家充滿活力、穩步成長的公司，歡迎在這裡找到屬於自己的舞台！ ●2008年10月股票掛牌上櫃 (股票代號3570) ●連續四年營收超越10億元 ●薪資水平在上櫃公司同業中名列前五名 ●擁有最完整的技術能量，每年客戶群超過2000家以上 ●是台灣產業涵蓋最廣的繪圖軟體解決方案代理商 ⭕ 工作內容 1. 協助專案規劃執行╱追蹤╱管理。 2. 電腦輔助設計軟體操作經驗及概念。 3. 產品線教育訓練與技術文件製作。 4. 協助客戶問題處理。 5. 其他主管交辦事項 ⭕ 需求條件 1. 機械相關科系畢（無經驗可，公司提供完善培訓） 2. 具1年以上CAD實務經驗。 ⭕ 其他資訊 1. 薪資福利：依學、經歷面議核薪。 2. 上班時間：固定日班08:30-17:30 (含午休時間，彈性上下班30分)。 3. 依據公司經營狀況發放季獎金、年中分紅、年終獎金及員工酬勞等。

【在華邦，學習不設限，讓AI技術力與你的未來力同步成長!】 我們深信「人才永續」是企業創新的核心動能。華邦持續投資於數據素養與AI應用的培育，支持每一位人才掌握AI與數據應用的核心能力。 ．內部學習平台提供超過4,000堂線上課程，其中包含近850堂資料科學、人工智慧、數據思維與程式技術等多元主題，支援彈性自主學習 ．建立跨部門的 AI實作班與技術社群，定期舉辦研習與交流活動，讓知識轉化為實戰力 ．完善數據應用學習資源，結合資料呈現(Power BI、Tableau)、資料處理(Python、JMP)、流程自動化(Power Automate、UiPath)、AI助手(Copilot)，協助同仁有效以數據驅動決策與創新。 ．搭配專業語言學習平台，提供學習補助與資源，鼓勵同仁持續進修，拓展國際視野 無論你是技術新秀還是資深專才，華邦鼓勵所有領域都能與AI結合，與國際接軌。持續精進、突破自我！ 【邀請您將104履歷同步上傳至華邦官方網站，將使您的履歷優先被主管看見】此職缺履歷登錄網址:https://bit.ly/4mhJmcL [職位簡介] 主導 CAD 團隊內部的 AI 應用發展策略，負責分析工作流程痛點、規劃 AI 導入計畫、整合跨部門資源，並協助帶領 AI 工程團隊實作與部署。 [工作內容] 1. 規劃 AI 在 CAD 領域的導入策略，建立技術 roadmap 2. 與設計部門、IT、資料科學小組協作，識別 AI 導入場景並取得實作資源 3. 管理 AI 專案時程與風險，追蹤模型成效並推動落地應用 4. 主導數據資源整合與標註流程設計 5. 指導 AI 工程師技術路線與開發優先順序

【在華邦，學習不設限，讓AI技術力與你的未來力同步成長!】 我們深信「人才永續」是企業創新的核心動能。華邦持續投資於數據素養與AI應用的培育，支持每一位人才掌握AI與數據應用的核心能力。 ．內部學習平台提供超過4,000堂線上課程，其中包含近850堂資料科學、人工智慧、數據思維與程式技術等多元主題，支援彈性自主學習 ．建立跨部門的 AI實作班與技術社群，定期舉辦研習與交流活動，讓知識轉化為實戰力 ．完善數據應用學習資源，結合資料呈現(Power BI、Tableau)、資料處理(Python、JMP)、流程自動化(Power Automate、UiPath)、AI助手(Copilot)，協助同仁有效以數據驅動決策與創新。 ．搭配專業語言學習平台，提供學習補助與資源，鼓勵同仁持續進修，拓展國際視野 無論你是技術新秀還是資深專才，華邦鼓勵所有領域都能與AI結合，與國際接軌。持續精進、突破自我！ 【邀請您將104履歷同步上傳至華邦官方網站，將使您的履歷優先被主管看見】此職缺履歷登錄網址:https://bit.ly/4mmbZ92 [工作內容] 1. Develop and maintain DRC related Calibre SVRF/TVF rule deck and tech file. 2. Develop and maintain dummy-fill utility to enlarge margin of processes. 3. Support designer/layout to fix design rule related issue. 4. Maintain Laker GUI for layout users. 5. Build and optimize automation flows (Python/TCL/Perl).