「數位IC後段APR工程師/技術經理 (新竹)」的相似工作

This vacancy is open for talent pool collection. We will contact you if we have proper vacancies that fit with your profile. Job Mission Represent manufacturing and act as gatekeeper from manufacturing to D&E function Add value in overall manufacturing processes such as forming, machining, joining, and assembling Job Description Contribute to the solution of faults and takes the necessary initiatives and practical decisions to ensure zero repeat Identify gaps and drive assigned process improvement projects and successful delivery Initiate and drive new procedure changes and projects Develop and maintain networks across several functional stakeholders Prioritize works and projects based on business situation Transfer knowledge and train colleagues on existing and newly introduced products Education Master degree in technical domain (e.g. electrical engineering, mechanical engineering, mechatronics) Experience 3-5 years working experience in design engineering Personal skills Show responsibility for the result of work Show proactive attitude and willing to take initiative Drive for continuous improvement Able to think outside of standard processes Able to work independently Able to co-work with different functional stakeholders Able to demonstrate leadership skills Able to work in a multi-disciplinary team within a high tech(proto) environment Able to think and act within general policies across department levels Diversity and inclusion ASML is an Equal Opportunity Employer that values and respects the importance of a diverse and inclusive workforce. It is the policy of the company to recruit, hire, train and promote persons in all job titles without regard to race, color, religion, sex, age, national origin, veteran status, disability, sexual orientation, or gender identity. We recognize that diversity and inclusion is a driving force in the success of our company. Need to know more about applying for a job at ASML? Read our frequently asked questions.

【職務說明】 Familiar with APR (ICC) flow from floorplan , power plan , placement , cts , routing , timing analysis and fixed , IR_Drop analysis , physical verification 【擅長工具】 Shell、Perl、TCL、EDA 【其他條件】 1.Familiar with hierarchical and/or low power design flow相關尤佳 2.Familiar with process node 40nm , 28nm , 12nm尤佳 3.Familiar with EDA tool ICC / ICC2 / innovus , primetime , Calibre , Redhawk , Tweaker 尤佳 4.Familiar with TCL/Perl/shell script programming 相關尤佳 5.1年以下工作經驗者，在學期間參加過專題比賽者尤佳

負責 3D-IC Interposer 與類比 IP 佈局設計 (Virtuoso / Allegro)，確保電性與實體規格，優化設計流程。 熟悉 Layout tools、Foundry PDK為佳。

1. Analog mixed signal IC layout 2. 熟悉IC Layout tool 3. 熟悉先進製程

請務必投遞官網(12438): https://careers.synopsys.com/job/hsinchu/applications-engineering-staff-engineer-ic-validator/44408/84710683632 You Are: You are an innovative and resourceful engineer with a deep curiosity for solving complex technical challenges at the intersection of hardware and software. With a strong foundation in Electronic Engineering, Computer Science, or a related field, you are adept at leveraging your programming expertise—whether in Python, Tcl, Perl, or similar languages—to streamline and enhance engineering workflows. Your experience within UNIX/Linux environments equips you to navigate high-performance computing scenarios with ease. You thrive in collaborative, cross-functional teams and are energized by the opportunity to work closely with top-tier foundry partners and leading fabless companies. Your keen understanding of physical verification flows—such as DRC, LVS, PERC, FILL, and DFM—sets you apart, and you are eager to deepen your expertise in SoC physical design enablement, process effect analysis, and signoff. You are detail-oriented, capable of producing clear technical documentation, and communicate with clarity and empathy across diverse audiences. What You’ll Be Doing: 1.Delivering advanced physical verification solutions (DRC/LVS/PERC/Fill) for top-tier foundries and key fabless customers, ensuring high-quality silicon signoff. 2.Developing and validating process design kits (PDKs) and verification methodologies in collaboration with R&D and customer teams. 3.Partnering with R&D to innovate and improve Synopsys tools and flows, contributing to the evolution of physical verification technologies. 4.Providing hands-on customer support, troubleshooting issues, and delivering timely resolutions that enhance customer satisfaction and product adoption. 5.Coordinating with internal teams, including product managers and end-users, to align on best practices and ensure seamless integration of new technologies. 6.Documenting technical solutions, validation methods, and customer workflows for knowledge sharing and process improvement. 7.Staying up to date on industry trends and applying new insights to continuously optimize verification processes and tools. The Impact You Will Have: Accelerate the adoption and success of Synopsys physical verification products in leading-edge semiconductor manufacturing processes. Drive the development of robust PDKs and methodologies that enable customers to achieve first-time-right silicon. Enhance the quality and reliability of Synopsys verification tools through direct feedback and collaborative innovation with R&D teams. Strengthen Synopsys’ reputation as a trusted partner to top-tier foundries and fabless customers worldwide. Facilitate faster product cycles and reduced time-to-market for customers by delivering efficient and effective signoff solutions. What You’ll Need: BS or MS degree in Electronic Engineering, Computer Science, or a related field. Proficiency in at least one programming language, such as Python, Tcl, or Perl. Hands-on experience with UNIX/Linux environments and command-line tools. Familiarity with physical verification flows (DRC, LVS, PERC, FILL, DFM) and understanding of complex layout/electrical design rules. Strong investigative, analytical, and problem-solving abilities, with a passion for learning new technologies. Ability to produce clear, concise technical documentation and validation reports. Prior knowledge of tool/runset development/support and experience with SoC physical design is a plus.

1. 車用IC驅動程式單元測試/整合測試/品質測試 2. 測試案例與維護 3. 車用流程認證文件撰寫 4. 自動化測試程序撰寫與維護

1.Analog and mixed mode circuit layout and verification 2.Co-work with designer for layout floor planning,routing and physical verifications 3.command file maintain

1. ARM CPU design physical implementation 2. ARM CPU power and timing sign off 3. Physical design flow enhancement for high-speed CPU

1. 負責IC版圖的自動佈局佈線、優化和驗證。 2. 確保IC佈局符合Circuit Designer設計需求及產品、製程、電氣的規範。

1. 熟練Autocad 電腦繪圖操作 2. 具備介面協調討論能力。 3. 其他主管交辦行政事項。

1. Knowledgeable in power analysis and IR/EM methodologies, with hands-on experience using Ptpx, Redhawk, or Voltus for power and IREM evaluation. 2. Familiar with the integrated circuit (IC) design flow, capable of performing design, optimization, and verification using tools such as ICC2 or INNOVUS. 3. Experience in developing automation scripts using Python, Perl, TCL, or Shell is a strong plus. 4. Experienced in IO/IP planning, including bump/PAD placement and RDL routing is a plus. 5. Experienced in fundamental circuit structures (e.g., standard cells, IO), with the ability to simulate basic circuits using Hspice or Spectre is a plus.

應用工程師，提供業務技術支援、產品應用與部署，幫助客戶成功使用我們的工具。可以透過與客戶的互動來共同學習和成長，在與不同的客戶溝通過程中，您不僅可以增強您的技術知識，還可以增加軟體的知識。 工作內容 1. 產品介紹與定期更新產品資訊給客戶 2. 與RD合作改善產品效能以及產品流程 3. 幫助客戶如何使用公司產品與協助客戶整合設計資料到公司產品進行分析 4. 提供業務技術支援、產品應用與部署，幫助客戶成功使用我們的工具

Analog IC Layout

【在華邦，學習不設限，讓AI技術力與你的未來力同步成長!】 我們深信「人才永續」是企業創新的核心動能。華邦持續投資於數據素養與AI應用的培育，支持每一位人才掌握AI與數據應用的核心能力。 ．內部學習平台提供超過4,000堂線上課程，其中包含近850堂資料科學、人工智慧、數據思維與程式技術等多元主題，支援彈性自主學習 ．建立跨部門的 AI實作班與技術社群，定期舉辦研習與交流活動，讓知識轉化為實戰力 ．完善數據應用學習資源，結合資料呈現(Power BI、Tableau)、資料處理(Python、JMP)、流程自動化(Power Automate、UiPath)、AI助手(Copilot)，協助同仁有效以數據驅動決策與創新。 ．搭配專業語言學習平台，提供學習補助與資源，鼓勵同仁持續進修，拓展國際視野 無論你是技術新秀還是資深專才，華邦鼓勵所有領域都能與AI結合，與國際接軌。持續精進、突破自我！ 【邀請您將104履歷同步上傳至華邦官方網站，將使您的履歷優先被主管看見】此職缺履歷登錄網址:https://bit.ly/4eYYFVa [工作內容] 1. Custom Library Management: Creating and maintaining Cadence/ Symbol Lobraries tailored for Flash memory, ensuring accuracy for both CDL and simulation. 2. Design Flow Automation: Driving automation initiatives to streamline and enhance Flash memory design processes. 3. Version Control Administration: Managing our global design platform and version control system for seamless collaboration and data integrity. 4. EDA Environment Optimization: Maintaining and improving our EDA tool integration and performance to provide a robust workspace.

【成為円星人】 円星科技由一群專業與充滿熱情的夥伴創立於2011年，為積體電路矽智財設計服務業之新秀，秉持著『成為半導體業最值得信賴之IP公司』的願景，追求永續經營與成長。 誠摯歡迎您成為円星人，加入我們，站上國際舞台！ 一起共同打拚，以精品文化之精神，創造價值，追求卓越！ 【職務簡介】 M31主要業務為向 IC 設計業者和晶圓代工廠授權 IP，此職務為負責支援開發IP的電腦輔助設計CAD職缺。 【將負責的工作內容】 1. PDK QA and maintenance. 2. design porting flow development. 3. EMIR flow development and maintenance. 3. Schematic related tools maintenance and automation programming. 4. IC Layout related tools maintenance and automation programming. 【條件與特質】 1. 擅長工具: - Python - TCL - Virtuoso skill - Experience with Synopsys Custom Compiler is a plus - Experience with Cadence Virtuoso is a plus - Experience with EMIR tool is a plus 2. 有 Analog CAD 相關工作經歷 2 年以上 3. 電機電子/資訊工程相關科系碩士畢業 如果您有以上相關經驗且對此職缺有興趣，歡迎投遞您的履歷！

我們正在尋找一位細心且積極學習的 Layout 工程師 加入我們的團隊。此職位將參與 IC 及封裝設計的物理佈局工作，並與設計、製程及驗證團隊密切合作，確保設計品質與時程。 這是一個絕佳的機會，讓你在專業領域中持續成長，並與經驗豐富的工程師一同合作，學習最先進的技術與流程。 主要工作內容： • 協助執行 IC 佈局設計，包括 floorplanning、placement、routing 及驗證。 • 參與 Package Layout 設計，並與封裝工程師合作完成設計需求。 • 使用 Allegro 等工具進行封裝佈局設計與修改。 • 執行 DRC、LVS、ERC 等設計檢查，確保設計符合規範。 • 支援 Tape-out 相關流程與文件準備。 • 撰寫與維護設計流程文件與佈局規範。 • 積極參與團隊討論與技術交流，分享學習成果並協助他人。 基本資格： • 電機、電子、資訊工程或相關科系學士學位。 • 具備 2 年以上 Package Layout 設計經驗。 • 熟悉 Allegro 或其他封裝佈局工具。 • 具備基本 IC 佈局知識，並願意學習 Analog/Digital Layout 技術。 • 良好的溝通能力與團隊合作精神。 • 細心負責，能在時程壓力下完成工作。 你將加入的團隊： 我們是一個重視 協作與知識分享 的團隊，鼓勵開放溝通與跨部門合作。你將有機會參與多樣化的專案，並在導師與資深工程師的指導下快速成長。我們提供技術培訓、職涯發展規劃，以及參與國際合作的機會，幫助你在職涯中持續進步。

1.Support and maintain EDA tools and flows used in the digital IC implementation. 2.Design and develop methodologies, automation scripts, and design flow. 3.Manage version control system (Git/SVN), issue tracking system, and CI/CD flow. [Requirement] 1.Python/Perl/TCL/Shell programming skills. 2.Familiar with EDA tools for IC design flow. 3.Basic knowledge of Verilog or SystemVerilog HDL.

1.Fully custom IC layout for analog 2.Channel or whole chip integration 3.Responsible for layout design,layout verificaion and tapeout.

1. Ensure PKG design is optimized with SI/PI/Thermal requirements. 2. Create the PKG/RDL/Subtract SI 3D modeling and perform extraction of S-Parameters and RLGC model. 3. Full-wave modeling of VIAs, Connectors, Package and PCB channels, components using 3D full-wave EM tools. 4. Provide the CM(Construction rules) and Design Rules(guidelines) for the PKG/RDL/Subtract design. 5. Provide the Substrate manufacturing process and material property. 6. SI(Signal integrity) simulation and optimization on package stack-up, power/ ground plane assignment and optimization, decoupling cap locations to minimize power ground noise. 7. PI(Power integrity) analysis for state of art package/system designs, which include but not limited to package layout model extraction, transient noise analysis to meet the silicon noise spec, decoupling strategy and analysis. 8. CTK(Crosstalk) analysis and reduction on-package considering mutual-effect by on-die, on-silicon interposer and on-PCB. 9. SSN(Simultaneous Switching Noise)/SSO analysis for I/O (DDR5/4/3, LPDDR5/4/3, etc.) power domain. 10. Eye diagram(ZRZ/PAM4) and jitter analysis for CPS(Die Chip-PKG-System PCB) co-simulations. 11. Familiar with trade-offs among package cost, technologies, design, performance, power, and thermal requirements. 12. Familiar with assembly and substrate manufacturing process is a plus. 13. Familiar with programming/scripting in Java, VBScript, PERL, TCL, MatLab and/or equivalent. 14. Experienced in SI PI automation tool development with Python or PyAEDT is a plus. 15. Working with ASIC/HW/Production team.

Analyzing voltage drop across the power grid under different operating conditions. Evaluating current density in metal interconnects and reliability concerns. Design, analyze, and improve power grids. Cross-functional collaboration – working with design, package, and verification teams. Automation and Flow Development – gaining hands-on experience in scripting to improve design efficiency.