「數位IC後段APR工程師/技術經理 (新竹)」的相似工作

1. Backend design tool and flow support - Innovus/ Calibre flow support 2. Timing / Power / SI convergence flow for backend flow 3. IR / EM flow tool usage support *備註：此職缺非研發替代役*

The VLSI Physical Design Engineer is responsible for implementing and optimizing the layout of integrated circuits (ICs) from netlist to GDSII. This role plays a key part in turning high-level logic designs into manufacturable silicon chips, ensuring electrical performance, area, and power (PPA) goals are met, and the physical verification results are good. Key responsibilities: 1. Derive full-chip and block-level physical design from netlist to tape-out (netilst to GDSII). 2. Floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and layout verifications. 3. Work closely with front-end design, DFT, and package teams to ensure design closure. 4. Sign-off on signal integrity, power integrity, reliability and manufacturability including performing static timing analysis (STA), IR drop analysis, EM analysis, and physical verification (DRC/LVS/DFM). 5. Analyze, optimize and resolve congestion, timing, power integrity and signal integrity issues. 6. Create and maintain physical design automation Tcl scripts, and flows development for design implementation. 7. Interface with EDA tool vendors and foundries to ensure design compliance and manufacturability.

1. Physical design and verification 2. Physical integration 3. Fully layout if necessary

招募導入水處理設備流程中計劃和設計階段裡使用CAD的工程師。 【工作內容】 ■ 接單前的計劃工作 ・應對客戶詢價與會議、系統研究、物料計算、成本計算、流程圖、配置設計、說明書製作、各種文件製作等。 ・優先考慮有志於將來向客戶提案最適合的系統和服務，並引領接單活動的過程工程師。 ・使用Inventor進行設備及設施的設計開發、導入及運營。 ・AutoCAD、Revit等軟體的操作。 ・進行Inventor操作及教育等相關工作。 ・經驗涵蓋流程圖、配置設計、說明製作、管道設計、採購設計、塔槽和機架設計、現場施工問題應對等，未來有機會成為專案設計leader！ 【魅力】 ・AI產業等蓬勃發展，目前半導體需求上升，業績穩定。 ・可以掌握日本半導體相關技術。 【法定項目】 ・勞健保 ・加班費 ・各種休假（特別休假、婚假、喪假、生理假、產檢假、陪產假、產假、育嬰假） ・退休金 【公司福利】 ・餐費津貼 ・員工旅遊（例：泰國） ・升遷制度 ・獎金（一年1次，平均2～3個月左右） ・出差津貼 ・員工聚餐

[駐點於知名科技公司服務] 希望你對最新科技技術和EDA工具有強烈的學習熱情，並且願意參與從SYN、APR、signoff到Foundation IP最新技術的開發，將這些技術應用到最前沿的產品中。 1. 設計流程維護： 維護和優化CAD參考流程，助力IC設計。 確保設計流程性能和準確性達到最佳狀態，產出更優質的成果。 2. 工具整合： 整合各種EDA工具（如Synopsys、Cadence、Mentor Graphics）到參考設計流程中。 確保不同工具之間的相容性和無縫操作，提升工作效率。 3. 文件編寫: 創建和維護參考流程的全面文件。 詳細記錄所有更改和更新，方便用戶未來參考。 4. 性能監控： 監控參考流程的性能，識別改進區域。 實施增強措施，提高流程效率，縮短設計週期時間。

負責 3D-IC Interposer 與類比 IP 佈局設計 (Virtuoso / Allegro)，確保電性與實體規格，優化設計流程。 熟悉 Layout tools、Foundry PDK為佳。

【職務內容】 ˙需具備HV經驗 Level Shifter（含 HV Device）、Charge Pump、Source Driver、OpAmp / DAC、TCON（含 Digital Layout + Clock Tree） ˙需具備3-5年Driver相關經驗 ˙需熟悉繞線（Routing） ˙Block-Level設計經驗可 ˙能讀懂 Calibre DRC command file 語法佳 ˙具備28/22nm HV製程經驗佳 ˙無需英文能力，全台灣團隊

【工作內容】 • 我們正在尋找具備先進製程經驗的 IC Layout 工程師，加入團隊後可以參與高階SoC /Analog IP 的實體實現，並負責以下工作： -Mixed-Mode FinFET Layout 設計與繪製，確保電路佈局在效能、面積與可靠性之間取得最佳平衡。 -進行 FinFET 製程相關的 DRC / LVS / ERC 驗證，確保設計符合法規與 Foundry 要求。 -熟悉 XRC & EM/IR 分析流程，進行可靠性評估，並針對潛在問題提出改善方案。 【職務條件】 • 必備條件：具備 FinFET 製程經驗，能獨立進行版圖設計與驗證。 -具備類比電路佈局經驗，了解電路特性與佈局考量，能與設計工程師密切合作。 -具備良好的溝通能力與團隊合作精神，能在專案時程內交付高品質成果。

Manage APR project Handle APR tasks Floorplan CTS PV STA IR…etc. 熟悉ICC2 or Innovus

投遞網址: https://careers.synopsys.com/job/hsinchu/r-and-d-engineering-sr-engineer/44408/85652406272 You Are: You are an experienced and passionate engineer with a profound curiosity for technology and a strong drive to solve complex problems. With a background in Electrical Engineering, Computer Science, Mathematics, or Physics, you have spent at least a decade mastering your craft, specializing in the intersection of software development and circuit design. Your expertise in C++/C programming, combined with a deep understanding of data structures, algorithms, and circuit simulation, sets you apart as a technical leader. You are comfortable navigating both analog and digital domains, leveraging your circuit design knowledge to drive innovation in electronic design automation (EDA) solutions. What You’ll Be Doing: • Designing, developing, and optimizing SPICE circuit simulation engines to enhance performance and accuracy. • Collaborating with global R&D teams to implement new algorithms and features for circuit analysis and optimization. • Analyzing and resolving challenging functional and performance issues in circuit simulation software. • Providing expert customer support, addressing technical inquiries, and guiding users through complex simulation problems. • Interpreting customer requirements and translating them into technical solutions and product enhancements. • Preparing and delivering technical presentations and documentation to both internal stakeholders and external customers. • Staying current with emerging trends in EDA, circuit simulation, and semiconductor technology to inform product direction. The Impact You Will Have: • Drive continuous improvement in Synopsys’ circuit simulation tools, directly impacting the success of semiconductor innovations worldwide. • Enable customers to achieve faster, more accurate chip designs by delivering robust and reliable simulation solutions. • Enhance the scalability and usability of EDA products, supporting the design of next-generation electronics. • Foster strong customer relationships through exceptional technical support and solution delivery. • Contribute to a collaborative, high-performance R&D culture that values knowledge sharing and creative problem-solving. • Shape the roadmap of Synopsys’ industry-leading simulation technologies through your insights and expertise. What You’ll Need: • MS or PhD in Electrical Engineering, Computer Science, Mathematics, Physics, or a related field. • 10+ years of hands-on experience in software engineering or circuit design. • Strong proficiency in C++ and/or C, with a solid grasp of data structures and algorithms. • Deep understanding of analog and digital circuit design principles. • Proven ability to analyze and resolve complex software or hardware issues independently. • Excellent English communication skills, both written and verbal. Who You Are: • Analytical thinker with a systematic approach to troubleshooting and problem-solving. • Effective collaborator who thrives in diverse, multicultural teams. • Proactive communicator with strong presentation and interpersonal skills. • Adaptable and resilient in the face of technical challenges and evolving priorities. • Detail-oriented, with a passion for delivering high-quality, reliable solutions. • Customer-focused, with a commitment to understanding and meeting user needs. The Team You’ll Be A Part Of: You will join a dynamic and innovative R&D team dedicated to developing advanced SPICE circuit simulation software. Our team brings together experts in software engineering, circuit design, and EDA solutions, working collaboratively across continents to deliver cutting-edge products. We thrive on tackling complex engineering challenges and are committed to continuous learning, knowledge sharing, and supporting each other’s growth. Your contributions will directly influence the capabilities and success of Synopsys’ simulation tools, empowering customers around the world.

1.Analog & physical design flow/script development 2.IR/EM sign-off 3.Flip-chip design 4.Physical verification flow

1.Analog and mixed mode circuit layout and verification 2.Co-work with designer for layout floor planning,routing and physical verifications 3.command file maintain

1.對Calibre LVS/XRC/DRC command file 程式開發有興趣者 2.清楚IC Layout，善於溝通協調 3.具備IC Layout 或 TCL/TK 相關經驗

IC layout

我們正在尋找具 2-3年以上經驗的資深版圖工程師，能獨立負責 Analog/Mixed-Signal/SoC IP 及 Top-Level Layout。 需熟悉 layout tool、CMOS 製程與 DRC/LVS 驗證，具高速介面經驗佳。 此職位需規劃 Floorplan、Power/Clock Routing、跨部門協作。 曾參與完整 Tape-out 專案者優先。 職務內容： 1.Interface IP layout 2.Ensure DRC/LVS clean 3.Ensure DRC/LVS clean 4.Fix EM/IR issue 5.Layout environment setup 6.IO planning, placement and routing 7.Help designer to debug and support FIB plan

Job Summary: Layout Engineer will work directly and indirectly with Design / CAD / Layout Manager in development of Mixed-Signal and Analog Integrated Circuits. Individual perform job professionally and independently. The following are the requirements for this job function. Essential Functions: • Chip Planning • Project Schedule / Layout Schedule Estimation • Device Placement on block level according to matching requirements • Block implementations on Top Level • Top Level connections • Signal matching / sensitive nets shielding technique • Chip power / ground planning • Integration of Analog top with Auto-Placement-Routing • Pad / ESD rule and routing / connection • Database DRC & LVS verifications on either DIVA or Dracula basis • Chip Tape-out in accordance with company’s Tape-out Procedure • Positive Attitude Qualifications: • 3+ years Layout experience in Analog and/or Mixed-Signal Circuit Design • Ability to do chip plan, estimate die size and project schedule • Ability to resolve DRC & LVS data verification and tape out chip independently • Familiarity with fundamentals of analog processes • Experience with Cadence and/or VIRTUOSO tools preferable

1. 負責IC版圖的自動佈局佈線、優化和驗證。 2. 確保IC佈局符合Circuit Designer設計需求及產品、製程、電氣的規範。

1.Fully custom IC layout for analog 2.Channel or whole chip integration 3.Responsible for layout design,layout verificaion and tapeout.

⚠️特別說明：此職位需on-site在新竹清大創新育成中心辦公室，無提供遠端工作條件。 ✅主要職責： 1. 高效能記憶體子系統（DDR/LPDDR Subsystem）之整合、開發與驗證。 2. 參與GenAI SoC設計，包括架構規劃、RTL設計、模擬與驗證。 3. 配合後端設計團隊，進行時序分析與設計優化。 5. 進行設計文件撰寫與維護，確保設計過程符合公司開發流程。 6. 針對客戶需求，進行系統分析與客製化設計開發。 ✅基本要求： 1. 電機、電子、資訊工程相關科系畢業，學士以上學歷。 2. 具備5年以上數位IC設計經驗。 3. 熟悉 DDR PHY 架構、控制器、timing calibration與 training 流程 4. 熟悉SoC Bus Fabric設計，具備AXI、AHB等匯流排介面經驗。 5. 熟悉RTL設計 (Verilog / System Verilog)。 6. 了解前端設計流程，包括模擬、合成、時序分析等。 7. 良好的問題分析能力，具備團隊合作精神。 ✅加分條件： 1. 有參與過 LPDDR Subsystem Integration與Silicon Tape-out 並成功量產 2. 熟悉 Synopsys LPDDR、Cadence GDDR IP/Subsystem 3. 熟悉 UPF、低功耗設計流程 4. 熟悉 DFT 、Scan、BIST ✅ Why Join Us 1. 與頂尖技術團隊共事，參與高效能 AI/高速記憶體解決方案開發 2. 自主創新文化，提供技術發揮與產品影響力兼具的工作環境

1. FrontEnd flow development. 2. Project support and consultant. 3. Develop CAD utility, design automation 4. Work with different process nodes, develop the design flow and methodology