1. Front-end IC design flow development/maintain/support
2. Experience in front-end design flow and familiarity with Prime Time,Prime Closure,Fusion Compiler.
3.Good understanding of timing sign off,constraint and timing closure methodology.
Responsibilities:
• Develop integrated verification environment.
• Verify designs with system verilog and system verilog assertion.
• Build, maintain and upgrade testbenches and their components using UVM-based methods.
• Check functional coverage and code coverage
• Create controlled random testcases. Pre-debug and provide debug reports.
• Scripting experience using scripting languages like Perl and Python.
1. Design verification with SystemVerilog/UVM, C/C++
2. Integration test environment with VIP
3. Develop checker and scoreboard.
4. Verify design with SystemVerilog assertion.
5. Test plan for a verification task.
[Requirement]
1. Familiar with SystemVerilog HDL, OOP, Python, TCL, and shell programming.
2. Better to have SoC design and bus concept.
[job description]
Wolley is seeking candidates for a digital design engineer position. You will join an experienced team designing next-generation memory, storage controllers, and high-speed interface standard.
You will also contribute to design concept discussion, architecture definition, as well as design implementation.
‧ Architecture design and RTL implementation
‧ System bus and related peripheral designs
‧ SoC and emulation platform design
‧ SoC system performance analysis
[Requirement]
1. Bachelor's or Master's degree in Electrical Engineering or related fields
2. Familiar with RTL design, SystemVerilog, front-end design flow
3. The following working knowledge is desired:
* Python programming
* TCL scripting
* Universal Verification Methodology (UVM)
* Low power design and analysis
【主要工作內容】
1.Netlist to GDS, including floorplan/powerplan/physical synthesis/clock tree synthesis & routing
2.Chip level physical verification, including DRC/LVS/DFM & tapeout
3.IR-Drop analysis
【需求條件】
1.有使用過ICC/ICC2/laker, 曾做過fully layout & chip level PV
2.工作態度積極認真, 有獨自解決問題能力
Job Description:
In this position the individual will develop test environment, test plan, and test cases based on the product specification and related industrial standards. The individual will require initiating a test plan review with the team and updating the test plan accordingly. The candidate will require executing and developing the test cases based on test plan, debugging and reporting the test result to achieve full function coverage goal. The individual will require developing ASIC bench functional test programs and doing ASIC bring-up and ASIC bench testing.
The ideal individual must have proven ability to achieve results in a fast moving, dynamic environment. The candidate must have ability to coordinate priorities and initiatives and clear communication skill.
※ Job Contents:
1. DDR/HBM controller IP design
2. DDR/HBM IP customer support
3. Execute digital IP front-end flow
※ Requirements:
1. 3-years digital IC design experiences
2. Senior/Technical Manager: 8-years digital IC design experiences
3. Familiar with DDR protocol is a plus
4. Familiar with AMBA interface is a plus
5. Familiar with IC front-end design flow such as Lint/CDC, Synthesis, LEC/formality, PrimeTime STA is a plus
使用最新的IC驗證方法對晶心的CPU設計做高強度測試,以提升CPU設計的品質與完整度。此職務可以累積對計算機架構,微架構,與嵌入式系統的廣泛知識。具體內容包含:
* Understanding uarch of Andes processor designs
* Creating verification plans
* Implementing test environments
* Generating test cases
* Improving test coverage
* Identifying CPU bugs in various environments (simulation, FPGA, etc.)
* Test automation
* Performance benchmarking
Design CPU functional units.
Responsibilities
Defining micro-architecture of the functional units
Writing RTL codes of the functional units
Writing documents of the function units
Working with cross-division teams to resolve functional, performance, power, and frequency issues related to the functional units
Qualifications
Available to start work three months after being hired.
3+ years of recent experience with Verilog logic design
Knows CPU micro-architecture, e.g. instructions, pipeline, caches, MMU
Knows power consumption of digital circuits
Good communicator in verbal and writing in English
Job Description
We are seeking a highly skilled ASIC Verification Engineer to join our team in Chupei, Taiwan. In this role, you will be responsible for developing and implementing comprehensive verification strategies for complex ASIC designs, ensuring the highest quality and reliability of our semiconductor products.
Develop and execute verification plans for complex ASIC designs
Create and maintain testbenches using SystemVerilog and UVM
Design and implement efficient verification environments
Perform functional and formal verification of digital designs
Develop automated test scripts to improve verification efficiency
Analyze and debug design issues identified during verification
Collaborate with design engineers to resolve functional discrepancies
Generate detailed verification reports and documentation
Stay updated with industry trends and emerging verification methodologies
Contribute to the continuous improvement of verification processes and tools
Qualifications
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
5+ years of experience in ASIC verification with strong proficiency in SystemVerilog and UVM
Experience with Verilog, VHDL, and industry-standard simulation tools (e.g., Synopsys VCS, Cadence Xcelium)
Experience of CPU, GPU, NPU or HBM verification
Knowledge of formal verification techniques and tools
Strong debugging, problem-solving, and analytical skills
Solid understanding of digital logic design, computer architecture, and communication protocols
Excellent organizational skills with strong attention to detail
Good communication and teamwork skills in a fast-paced environment
DESCRIPTION:
1. Responsible for the physical design process of chip numbers from netlist to GDSII
2. Responsible for interaction with the front-end design team to realize the design convergence and optimization of the front and back ends; Comprehensive, static timing analysis
3. Floor planning, power planning and signoff, place and route, timing closure, chip static timing analysis and physical verification
4. IP integration, synthesis, verification and correction
5. Other Assigned Tasks delivered by the Line Manager
QUALIFICATIONS:
1. MS degree in EE or related.
2. Familiar with physical design flow, including hierarchical design and low power design is a plus
3. Familiar with EDA tools, such as SoC Encounter/INNOVUS/ICC/ICC2 is a plus
4. Familiar with computer languages such as Perl/TCL/C-shell
5. Self-motivated with good communication skills and team spirit
6. Ability to understand and articulate technical issues.
7. Fluent English is a plus.
8. Experience in 12/5nm design is a plus.