Responsibilities:
• Develop integrated verification environment.
• Verify designs with system verilog and system verilog assertion.
• Build, maintain and upgrade testbenches and their components using UVM-based methods.
• Check functional coverage and code coverage
• Create controlled random testcases. Pre-debug and provide debug reports.
• Scripting experience using scripting languages like Perl and Python.
1. Work on 3~7nm design implementation, methodology, and sign-off
2. Perform synthesis, DFT, floorplan, clock planning, place and route, timing closure, ECO, IR signoff, and physical verification
3. Manage schedule, resolve design and flow issues, drive methodologies and execution
1. Design verification with SystemVerilog/UVM, C/C++
2. Integration test environment with VIP
3. Develop checker and scoreboard.
4. Verify design with SystemVerilog assertion.
5. Test plan for a verification task.
[Requirement]
1. Familiar with SystemVerilog HDL, OOP, Python, TCL, and shell programming.
2. Better to have SoC design and bus concept.
[job description]
Wolley is seeking candidates for a digital design engineer position. You will join an experienced team designing next-generation memory, storage controllers, and high-speed interface standard.
You will also contribute to design concept discussion, architecture definition, as well as design implementation.
‧ Architecture design and RTL implementation
‧ System bus and related peripheral designs
‧ SoC and emulation platform design
‧ SoC system performance analysis
[Requirement]
1. Bachelor's or Master's degree in Electrical Engineering or related fields
2. Familiar with RTL design, SystemVerilog, front-end design flow
3. The following working knowledge is desired:
* Python programming
* TCL scripting
* Universal Verification Methodology (UVM)
* Low power design and analysis
【主要工作內容】
1.Netlist to GDS, including floorplan/powerplan/physical synthesis/clock tree synthesis & routing
2.Chip level physical verification, including DRC/LVS/DFM & tapeout
3.IR-Drop analysis
【需求條件】
1.有使用過ICC/ICC2/laker, 曾做過fully layout & chip level PV
2.工作態度積極認真, 有獨自解決問題能力
【工作內容】
• Work with team members and apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market
• Provide the technical leadership to the DV team for the project
• Work independently on various DV tasks and provide technical guidance to the DV team.
• Be involved technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup
【職務條件】
• Master’s degree in Electrical Engineering, Computer Science, or related.
• Good understanding of ASIC design verification flow.
• RTL coding with Verilog/System Verilog and familiar with front-end design flow and C/C++ programming experiences.
• Knowledge of Perl, OVL, SVA, SV, UVM, OVM, script programming, etc.
【其他條件】
• MSEE with a minimum of 5 years, or BSEE with a minimum of 8 years of experience in digital ASIC/SOC design verification
• MS/BS degree in EE or CS with expertise in digital IP/SOC design verification.
使用最新的IC驗證方法對晶心的CPU設計做高強度測試,以提升CPU設計的品質與完整度。此職務可以累積對計算機架構,微架構,與嵌入式系統的廣泛知識。具體內容包含:
* Understanding uarch of Andes processor designs
* Creating verification plans
* Implementing test environments
* Generating test cases
* Improving test coverage
* Identifying CPU bugs in various environments (simulation, FPGA, etc.)
* Test automation
* Performance benchmarking
Design CPU functional units.
Responsibilities
Defining micro-architecture of the functional units
Writing RTL codes of the functional units
Writing documents of the function units
Working with cross-division teams to resolve functional, performance, power, and frequency issues related to the functional units
Qualifications
Available to start work three months after being hired.
3+ years of recent experience with Verilog logic design
Knows CPU micro-architecture, e.g. instructions, pipeline, caches, MMU
Knows power consumption of digital circuits
Good communicator in verbal and writing in English
Job Description
We are seeking a highly skilled ASIC Verification Engineer to join our team in Chupei, Taiwan. In this role, you will be responsible for developing and implementing comprehensive verification strategies for complex ASIC designs, ensuring the highest quality and reliability of our semiconductor products.
Develop and execute verification plans for complex ASIC designs
Create and maintain testbenches using SystemVerilog and UVM
Design and implement efficient verification environments
Perform functional and formal verification of digital designs
Develop automated test scripts to improve verification efficiency
Analyze and debug design issues identified during verification
Collaborate with design engineers to resolve functional discrepancies
Generate detailed verification reports and documentation
Stay updated with industry trends and emerging verification methodologies
Contribute to the continuous improvement of verification processes and tools
Qualifications
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
5+ years of experience in ASIC verification with strong proficiency in SystemVerilog and UVM
Experience with Verilog, VHDL, and industry-standard simulation tools (e.g., Synopsys VCS, Cadence Xcelium)
Experience of CPU, GPU, NPU or HBM verification
Knowledge of formal verification techniques and tools
Strong debugging, problem-solving, and analytical skills
Solid understanding of digital logic design, computer architecture, and communication protocols
Excellent organizational skills with strong attention to detail
Good communication and teamwork skills in a fast-paced environment
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Hardware design verification :
• Develop verification environment.
• Co-work with hardware designers to verify designs with system verilog and system verilog assertion.
• Building, maintaining testbenches and their components using UVM-based methods.
• Functional coverage and code coverage.
• Generating the random testcases for NPU design,and providing debug reports.
• Develop the auto-verifying environment using scripting languages like Perl and Python.
Programming Languages: Strong programming skills in languages like System Verilog, Verilog and possibly high-level languages like C/C++.
Experience in AI/ML: In-depth knowledge of artificial intelligence and machine learning algorithms.
NPU Architecture: Proficiency in designing Neural Processing Unit architectures.
Parallel Processing: Understanding of parallel processing and optimization techniques for neural networks.
Team Collaboration: Effective communication and collaboration skills within a multidisciplinary team.
Problem-solving: Strong analytical and problem-solving skills to address complex design challenges.
Knowledge of Industry Trends: Awareness of the latest trends and advancements in NPU technology and AI hardware.
Results-Driven: A proactive and results-driven mindset, aiming for high-quality outcomes.
Ownership Mentality: Willingness to take ownership and responsibility for the design process.
Adaptability: Ability to adapt to evolving technologies and project requirements.
Advanced Degree: Typically, a relevant advanced degree (Master's or Ph.D.) in Electrical Engineering, Computer Science, or a related field.