高速 SERDES TX DRV 電路設計

工作內容 1. 高速介面 (SerDes) 類比電路設計 2. Circuit design of CTLE/CDR/DFE/PLL/HDMI2.1 TX /USB3.2 RX /USB3.2 TX

* Familiar with High-speed SerDes (高速介面) PHY design such as PCIE, USB3, SATA, MIPI, MPHY, HDMI, etc. * Circuit design

specification definition ★ Create behavior model for analog/digital evaluation ★ Compliance test for SerDes IP 【符合條件 (Qualifications)】：

1. Firmware and Software development 2. SERDES IP verification 3. System verification

工作職責 1.熟悉高速類比 SerDes 電路設計, 例如: CTLE, CDR, DFE, PLL, 以及 TX Driver 等 2.具有相關高速電路開發經驗 與熟悉Serdes 規格 3.加分條件: 具備有整合AI晶片與Serdes經驗 者

負責高速介面電路設計： 1.高速介面電路設計 2.PLL/DLL/CDR GHz PHY Design 3.類比IP設計(EQ, CDR, OP, OSC, Regulator, BandGap, ...) 4.具有整體晶片規畫能力

1. High-speed PHY TX(FFE, driver), RX(CTLE, DFE, CDR) and PLL design。 2. Communicate with digital, layout and system engineer。 3. Design verification/documentation/supporting。 4. PAM4 circuit design experience is a plus。

We are looking for a senior engineer to be part of the mixed-signal design team building next generation NVLINK. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. You will be responsible for the development and implementation of high speed interfaces, including TX/RX/Clocking/PLL. You will have hands on experience taking innovative integrated circuit designs at data rates of 50Gbps and higher from concept through silicon characterization. What you will be dong: - Define circuit requirements and complete design from schematic, layout, and verification to characterization. - Conduct schematic design of deep-submicron CMOS technologies using Spectre, Hspice or like. - Take responsibility for the architecture, transistor design and verification using industry standard EDA tools such as Cadence virtuoso. - Optimize circuit to meet the specifications for system performance. - Work with layout engineers by providing detailed floorplan and guidance for matching and high-speed routings. - Provide support for post-silicon bring-up and debugging. What we need to see: - Master of Science or foreign equivalent degree in Electrical Engineering, Computer Engineering or related field with strong analog design background. - Minimum 2 years analog design experience in industry - CMOS Analog / Mixed Signal Circuit Design Experience in deep sub-micron process (especially in FINFET) - Experience with design and verification tools (Cadence's IC design environment, analog circuit simulation tools like Spectre, HSpice, Finesim, XA) - Experience in crafting test bench environments for component and top level circuit verification - Behavioral modeling of analog and digital circuits - Strong debugging and analytical skills - Analog simulation for noise analysis, loop stability analysis, ac/dc/tran analysis, monte-carlo, etc. - Strong communication skills and ability & desire to work as a great teammate are huge plus. - All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, citizenship, disability or protected veteran status.

1.mixed mode circuit design 2.DC-DC and LDO circuit design 3.PLL & Serdes circuit design 4.ESD, Latch up & I/O circuit

之精神，創造價值，追求卓越！ 【職務簡介】 M31主要業務為向 IC 設計業者和晶圓代工廠授權 IP，此職務為負責高速介面 IP（High Speed Interface IP）, 包含USB. PCIE 等SERDES IP設計工程師職缺。

1. Ethernet SerDes高速介面數位設計 (USXGMII, 25G Base-R) 2. 依據系統規格, 執行架構設計以及撰寫硬體描述語言 (RTL), 和軟體同仁合作進行相關驗證 3. 具有高速介面或 high level

負責高速介面電路設計： 1.高速介面電路設計 2.PLL/DLL/CDR GHz PHY Design 3.類比IP設計(EQ, CDR, OP, OSC, Regulator, BandGap, ...) 4.具有整體晶片規畫能力

Serdes/AIP/IO layout

1. 網路通訊晶片功能驗證 (Ethernet SERDES, USB, PCIe) 2. SERDES PHY驅動程式開發與維護 3. 自動化測試工具開發與維護

1. High-speed PHY TX(FFE, driver), RX(CTLE, DFE, CDR) and PLL design。 2. Communicate with digital, layout and system engineer。 3. Design verification/documentation/supporting。 4. PAM4 circuit design experience is a plus。

1.mixed mode circuit design 2.DC-DC and LDO circuit design 3.PLL & Serdes circuit design 4.ESD, Latch up & I/O circuit

1. High Speed SerDes circuit Design 2. Receiver 3. Transmitter 4. CDR 5. CTLE 6. PLL

* Analog/Mixed signal IC design & architecture for SerDes, Adaptive Equalizer (CTLE/FFE/DFE), CDR, PLL, PHY, Transmitter,

Familiar with PLL circuit design, LC-VCO design Familiar with RX-CTLE/DFE TX-FFE circuit design Familiar with CDR circuit design Familiar wih analog BG/OTA/LDO circuit design Familiar with all digital CDR/PLL is a plus Familiar with on-chip inductor analysis is a plus