台北市內湖區2年以上專科以上待遇面議
【工作職責 / Responsibilities】
⦁ 設計與驗證電源解決方案 (DC/DC、LDO、PMIC),特別針對 SSD (Client/Enterprise/Datacenter) 電源架構,確保符合 PCIe、NVMe、OCP、SNIA、ONFI 等規範。
⦁ 支援 SSD 控制器、NAND (ONFI)、高速介面 (PCIe Gen4/Gen5/Gen6, DDR4/DDR5, LPDDR5/5X) 的電源應用與調適。
⦁ 進行電源測試:時序 (Power Sequencing)、突波電流 (In-rush Current)、低功耗模式 (PS0~PS4, ASPM, APST)。
⦁ 與研發/FAE/製造團隊協作,參與 SSD EVT/PVT 驗證,並協助完成 OCP/JEDEC/PCI-SIG/ONFI 合規測試。
⦁ 追蹤新技術與業界標準 (如 PCIe、DDR、OCP、JEDEC、SNIA、ONFI),並回饋市場需求。
⦁ Design and validate power solutions (DC/DC, LDO, PMIC), especially for SSD (Client/Enterprise/Datacenter) power architecture, ensuring compliance with PCIe, NVMe, OCP, SNIA, and ONFI standards.
⦁ Support power applications and optimization for SSD controllers, NAND (ONFI), and high-speed interfaces (PCIe Gen4/Gen5/Gen6, DDR4/DDR5, LPDDR5/5X).
⦁ Conduct power testing: sequencing, in-rush current, and low-power modes (PS0~PS4, ASPM, APST).
⦁ Collaborate with R&D/FAE/manufacturing teams, participate in SSD EVT/PVT validation, and assist in OCP/JEDEC/PCI-SIG/ONFI compliance testing.
⦁ Stay updated with new technologies and industry standards (PCIe, DDR, OCP, JEDEC, SNIA, ONFI), and provide feedback on market needs.
【任職要求 / Requirements】
⦁ 電子/電機相關學歷,學士以上。
⦁ 熟悉電源電路拓撲 (Buck, Boost, Flyback, LLC, LDO, PMIC)。
⦁ 熟悉電源測試與調試工具 (Oscilloscope, Power Analyzer, Load, VNA 等)。
⦁ 熟悉 PCB Layout 電源設計規範與 EMI/ESD/PI/SI 考量。
⦁ 具 SSD 系統電源設計與驗證經驗 (Client/Enterprise/Datacenter SSD) 者優先。
⦁ 2–5 年電源設計或應用工程相關經驗。
⦁ 熟悉 SSD 電源時序、功率分配與低功耗設計經驗者佳。
⦁ 英文技術文件閱讀與撰寫能力,良好跨部門溝通能力。
⦁ Bachelor’s degree or above in Electrical/Electronics Engineering or related fields.
⦁ Familiar with power circuit topologies (Buck, Boost, Flyback, LLC, LDO, PMIC).
⦁ Hands-on experience with power test/debug tools (oscilloscope, power analyzer, load, VNA, etc.).
⦁ Knowledge of PCB layout rules for power design, including EMI/ESD/PI/SI considerations.
⦁ Experience in SSD system power design and validation (Client/Enterprise/Datacenter SSD) is preferred.
⦁ 2–5 years of experience in power design or application engineering.
⦁ Knowledge of SSD power sequencing, distribution, and low-power design is a strong plus.
⦁ Ability to read/write technical documents in English and strong cross-functional communication skills.
【加分條件/Plus 】
⦁ 有 SSD (CFexpress, M.2, E1.S, E3.S, HHHL/FHHL AIC) 電源設計或應用經驗。
⦁ 熟悉 SSD 相關標準 (JEDEC JESD230、OCP v2.6、PCI-SIG、SNIA、ONFI)。
⦁ 有 FPGA/ASIC/SoC 電源設計或業界規範測試經驗。
⦁ 熟悉 Cadence/Allegro、SPICE、SIMPLIS 等模擬工具。
⦁Experience in SSD power design or applications (CFexpress, M.2, E1.S, E3.S, HHHL/FHHL AIC).
⦁Familiar with SSD standards (JEDEC JESD230, OCP v2.6, PCI-SIG, SNIA, ONFI).
⦁Experience in FPGA/ASIC/SoC power design or industry compliance testing.
⦁Familiar with simulation tools such as Cadence/Allegro, SPICE, SIMPLIS.