「Command File 工程師(新竹)」的相似工作

1. 具備 Layout 工作經驗，想挑戰SOC晶片(Mix mode / HV / SRAM / Power / ESD..)並有志往Physical design 發展者 2. 需懂ESD / 製程觀念 / 電路原理 3. 具Tapeout 量產經驗，獨立處理 Whole chip 能力尤佳 4. 熟以下流程尤佳：Laker L3+ HSIM simulation + IREM分析 5. 強烈要求穩定性高，積極度高，做事態度需具備高度 Commitment 決心與毅力，具備高度 EQ/AQ，擁有團隊合作的精神 6. 工作地點：此職缺在【台南(樹谷園區)、新竹】皆設有相關單位。

1.電子相關領域佳 大學/碩士 ,Fully IC Layout工作經驗尤佳 2.需修過VLSI設計概論、半導體器件等相關課程，熟VLSI設計，懂類比設計，半導體元件物理尤佳 3.對於IC設計後段 , Physical Design 領域有濃厚興趣者，懂IR-Drop/EM analysis，或有興趣者尤佳 4.對於 Parasitical device effect prevent, ESD/EMI physical design , HV Design/Layout , IC Layout Reliability有濃厚興趣者 5.此職務需要穩定性高，積極度高，做事態度需細心嚴謹 , 需具備高度 EQ/AQ，擁有團隊合作的精神 6.對高複雜度的Whole chip 整合有興趣者

主要職責 1. Layout設計與實作 根據電路圖（schematic）進行analog/mixed-signal或digital layout佈局設計 執行模組層級（block-level）與頂層（top-level）layout整合 負責元件placement、routing、floorplan與metal layer規劃 2. DRC/LVS檢查與修正 使用EDA工具執行設計規範檢查（DRC, LVS） 修正版圖與設計間的不一致，確保layout正確無誤 執行ERC（Electrical Rule Check）、ANT（Antenna Check）等檢查 3. 協同工作與設計優化 與電路設計工程師合作進行版圖最佳化（例如降低parasitics、改善matching） 針對layout提出建議以達到功耗、面積與性能的最佳平衡 4. 製程與封裝考量 根據製程規範（Design Rule）進行設計，考量DFM（Design for Manufacturability）與封裝需求 了解不同foundry的PDK（Process Design Kit）限制與應用

1. Front-end IC design flow development/maintain/support 2. Experience in front-end design flow and familiarity with Prime Time,Prime Closure,Fusion Compiler. 3.Good understanding of timing sign off,constraint and timing closure methodology.

1. Knowledge and experience of circuit design guideline, latch up, EM and ESD checking rule. 2. Calibre DRC/LVS/PERC Command File maintain and writing. 3. Physical Verification flow enhancement and deployment. 4. CAD Utility development. 5. Soft skill ability like TCL, Perl, shell script

RTL design/Verilog behavior model development APR flow support CAD/CAE internal flow/script maintenance

1. IC設計軟體使用介面自動化程式開發(所指的設計軟體包含益華電腦[Cadence]，新思科技[Synopsys]，明導科技[Mentor] 公司所開發的IC 設計軟體)  操作介面開發之程式開發  操作流程整合之程式開發 所需技能 : 程式開發能力( 具Perl /Python/ Cadence Skill/ C-Shell/C 程式語言或有興趣者 ) 2. IC設計資料驗證程式開發  DRC /LVS /RCX 程式開發  電路模擬的測試程式開發 所需技能 : 程式開發能力( 指的是運用IC設計軟體內建指令所設計出的程式開發或有興趣者) 『具工作經驗者，薪資另議』 

Digital IC design engineer - Familiar with Verilog RTL coding - Familiar with digital design flow (pre-layout simulation, timing constraint, synthesis, post-layout simulation) - Will be working on high speed Serdes IPs - Experience or interest in all-digital PLLs or clock-data recovery circuits is a big plus

1.Analog & physical design flow/script development 2.IR/EM sign-off 3.Flip-chip design 4.Physical verification flow

Full Customer Layout

我們正在尋找一位熱情、有經驗的EDA應用工程師，加入我們充滿創新和技術挑戰的團隊。這位工程師將與台灣地區的客戶及合作夥伴緊密合作，提供最新的電子設計自動化工具和技術支援，以實現客戶的設計最佳化及效率提升。 職責： 與客戶端的工程師密切合作，了解其設計需求，提供EDA工具相關的技術支援。 協助客戶優化和自動化設計流程，以提高生產力和效率。 在EDA工具中執行模擬和分析，確保客戶設計的性能、功耗和可靠性符合要求。 解決客戶在設計過程中遇到的技術挑戰，提供解決方案以滿足其產品開發目標。 資格要求： 學士或以上學歷，專業領域包括電子工程、計算機工程或相關領域。 具備良好的問題解決和溝通能力，能夠有效協作並在客戶團隊中發揮領導力。 對IC設計、半導體及EDA產業有濃厚興趣，並追求不斷學習和專業成長。 必要條件： 具有相關EDA工具（如Cadence、Synopsys、Mentor Graphics等）的使用經驗。 熟悉硬體描述語言（SystemVerilog、Verilog、VHDL）和模擬工具。 英文聽說讀寫中等以上

【主要工作內容】 1.Netlist to GDS, including floorplan/powerplan/physical synthesis/clock tree synthesis & routing 2.Chip level physical verification, including DRC/LVS/DFM & tapeout 3.IR-Drop analysis 【需求條件】 1.有使用過ICC/ICC2/laker, 曾做過fully layout & chip level PV 2.工作態度積極認真, 有獨自解決問題能力

1.Analog and mixed mode circuit layout and verification 2.Co-work with designer for layout floor planning,routing and physical verifications 3.command file maintain

【在華邦，學習不設限，讓AI技術力與你的未來力同步成長!】 我們深信「人才永續」是企業創新的核心動能。華邦持續投資於數據素養與AI應用的培育，支持每一位人才掌握AI與數據應用的核心能力。 ．內部學習平台提供超過4,000堂線上課程，其中包含近850堂資料科學、人工智慧、數據思維與程式技術等多元主題，支援彈性自主學習 ．建立跨部門的 AI實作班與技術社群，定期舉辦研習與交流活動，讓知識轉化為實戰力 ．完善數據應用學習資源，結合資料呈現(Power BI、Tableau)、資料處理(Python、JMP)、流程自動化(Power Automate、UiPath)、AI助手(Copilot)，協助同仁有效以數據驅動決策與創新。 ．搭配專業語言學習平台，提供學習補助與資源，鼓勵同仁持續進修，拓展國際視野 無論你是技術新秀還是資深專才，華邦鼓勵所有領域都能與AI結合，與國際接軌。持續精進、突破自我！ 【邀請您將104履歷同步上傳至華邦官方網站，將使您的履歷優先被主管看見】此職缺履歷登錄網址:https://bit.ly/4mmbZ92 [工作內容] 1. Develop and maintain DRC related Calibre SVRF/TVF rule deck and tech file. 2. Develop and maintain dummy-fill utility to enlarge margin of processes. 3. Support designer/layout to fix design rule related issue. 4. Maintain Laker GUI for layout users. 5. Build and optimize automation flows (Python/TCL/Perl).

1.IC 之規格訂定與驗證 2.NB面板 DP相關驗證 3.FPGA系統設計與驗證 4.客戶端筆電面板模組驗證與Design In技術支援 5.具備C# 或 C++ 能力, 以開發IC驗證軟體與IC驗證系統 6.工作地點：台南

(1)Must have BS in CS/EE of relevant experience in IC design field. (2)Familiar with IC design flow, placement and route (P&R), and layout. (3)Circuit knowledge and logic design relevant experience would be a plus.

Introduction to the job Do you like challenges and do you want to work in a fast pacing supply chain environment to support some of the biggest semiconductor companies worldwide? Are you familiar with Logistics Operations and like to managing urgent demands on a daily basis?  If this sounds like you and if you have a strong customer oriented mindset, here is your mission. Role and responsibilities For our Global Operations Center in Taiwan we are searching for Supply Chain Professionals. You fulfill the demand of our customers for spare parts and tools for their maintenance activities on some of the most complex machines in the right quantity and at the right time & cost. Time is of the essence to ensure a seamless production of our customers without interruptions on our machines. -Handling of urgent material requests from worldwide customers in a rolling 24/7 shift system with the right customer focus, while meeting all milestones related to communication and execution -Monitoring of worldwide shipments  -Ability to resolve complex issues and drive improvements to further optimize processes -Ability to support escalations and provide communication proposals for review -Constructive and reliable communication with worldwide stakeholders from all departments within ASML -This position requires shift work. Education and Experience Bachelor's Degree in related subject i.e. Supply Chain Management, Information Science, Engineering etc. preferred -Minimum 1 year of relevant experience in an international company, semiconductor industry is preferred -A tactical thinker with strong interpersonal and communication skills -Analytical thinking and ability to organize and prioritize workload Skills Working at the cutting edge of tech, you’ll always have new challenges and new problems to solve – and working together is the only way to do that. You won’t work in a silo. Instead, you’ll be part of a creative, dynamic work environment where you’ll collaborate with supportive colleagues.  There is always space for creative and unique points of view. You’ll have the flexibility and trust to choose how best to tackle tasks and solve problems. To thrive in this job, you’ll need the following skills: -Stress-resistant; act under high pressure -Flexible; willing to go the extra mile for the customer -Excellent professional communication in English, written and oral -Drive for results; does not stop until solution has been found, even when obstacles arise -Team player -Change management competencies -Convincing, pro-active and “can do” mentality -Cultural awareness -Experience with ERP system(s), SAP R/3 knowledge preferred -Ability to prioritize Diversity and inclusion ASML is an Equal Opportunity Employer that values and respects the importance of a diverse and inclusive workforce. It is the policy of the company to recruit, hire, train and promote persons in all job titles without regard to race, color, religion, sex, age, national origin, veteran status, disability, sexual orientation, or gender identity. We recognize that diversity and inclusion is a driving force in the success of our company. Need to know more about applying for a job at ASML? Read our frequently asked questions.

Position Description Develop PEGASUS/PVS DRC, FILL, LVS, LPE rule decks and RCX flow for worldwide foundries. Manage onsite technical qualification to ensure both PEGASUS/PVS decks and tools are officially qualified by foundries. Collaborate closely with early adoption customers to track and resolve product issues Establish communication channels with R&D to capture customer needs and requirement spec. Work with R&D to enhance and improve PEGASUS/PVS, positioning it as a leading edge Physical Verification tool Position Requirements B.S. in Electrical Engineering (EE), Computer Science (CS), or related area (or equivalent) and 3 - 5 years of experience with Physical Verification tool support/development OR M.S. in EE or CS, or related area (or equivalent) and 1 - 3 years of experience with Physical Verification tool support/development Profound knowledge with Foundry Design Rules and semiconductor fabrication process Ability to develop PEGASUS/PVS rule deck for worldwide foundries, ensuring quality, performance, and compliance with schedules and qualification requirements. Proficiency in TCL and PERL scripting is required Strong English communication skills. Software development experience preferred; familiarity with Cadence SKILL programming is a plus. Experience with IC design and CAD support is advantageous.

1. 需具備類比IC Layout、BCD Prcoess整合經驗。 2. 需負責全晶片整合佈局和驗證 3. 熟悉Virtuoso, Laker, Calibre使用 4. 此職務上班地點在新竹辦公室

1.Fully custom IC layout for analog 2.Channel or whole chip integration 3.Responsible for layout design,layout verificaion and tapeout.