「Senior Digital Design Engineer」的相似工作

The successful candidate will work with team members and apply his/her design techniques to work on different phases of complex logic design for ASIC/SOC project. The role will include working on the following tasks from time to time: HDL coding, documentation, RTL quality check, cooperate with back-end engineer etc. 【Key Responsibilities】 - Responsible for front-end digital logic design in ASIC/SOC projects. - Perform HDL coding (Verilog/SystemVerilog). - Prepare and maintain design documentation (specifications and design documents). - Conduct RTL quality checks (Lint, CDC, power analysis, etc.). - Collaborate with Backend/Physical Design engineers to achieve timing closure. 【Core Requirements】 - Education/Experience: Master’s degree with ≥ 2 years, or Bachelor’s degree with ≥ 3 years of digital ASIC/SOC design experience. - RTL Design: Proficient in RTL coding using Verilog/SystemVerilog or VHDL. - TO / Front-End Flow: Familiar with front-end design flow, including synthesis, Lint, CDC, and STA. - EDA Tools: Experience with tools such as Lint, CDC check, and PrimeTime PX (power analysis). - Documentation: Ability to write design specifications and technical documents. - Collaboration: Work closely with the Design Verification (DV) team on IP verification. 【Preferred Qualifications】 - Familiarity with CPU architectures (x86/ARM/8051). - Knowledge of AMBA bus protocols (AXI/AHB/APB). - Understanding of PCIe protocol.digital IP/SOC design verification.

我們正在尋找一位資深人員，帶領FPGA專案開發，包含主機板時序控制、客戶FPGA專案需求開發設計，及FPGA實作上必要時需與軟硬體研發團隊成員進行協作。 工作內容： 1. 數位邏輯設計並熟悉RTL Coding架構。 2. 熟悉並使用Altera Quartus或Xilinx Vivado開發FPGA系統。 3. 熟悉主機板CPU power sequence control。 4. 熟悉影像方面的高速介面(SDI/HDMI)、DDR高速介面、PCIe、I2C、UART、SPI等介面應用。 5. SoC FPGA系統整合。 6. FPGA IP 整合及驅動程式開發。

Key responsibilities: • Perform IC design of FTDI products • Perform Verilog RTL design to meet product specifications and requirements • Perform front-end verification using UVM methodology • Work with Systems and Software engineers on FPGA verification • Perform Logic Synthesis, Static Timing Analysis • Lead DFT related activities - Scan Insertion, ATPG, Pattern Validation • Work with Physical designer to achieve timing closure • Work with test team in debugging production test issues • Help debug & correct any functional issues found in taped-out devices • Participate in design reviews, support ISO processes and documentation Additional responsibilities: a) Any reasonable task assigned by management and deemed to be within the individuals’ capabilities to ensure smooth running of the business. b) As this is an evolving business, ongoing change is an integral part of the position. Management will liaise with the individual on any fundamental change to work practices. The individual is required to embrace and adopt any change to working practices. Knowledge and skill requirements: • Degree/Master in Electrical/Electronic Engineering • 5 years or above experience in the area of digital IC design • Working experience from design to tape-out are essential • Experience in Verilog HDL and VHDL RTL design, OVM/UVM verification methodology , Logic Synthesis, DFT, ATPG, Timing Closure • Experience in using EDA tools from Cadence, Synopsys • Knowledge and working experience in one or more of the following: o Digital and mixed-signal design o USB interface products o Knowledge in connectivity technology such as USB, UART, SPI, I2C o Project Management Working conditions:  Working conditions are normal for an office environment.  Work requires willingness to work a flexible schedule.

【工作內容】 • Work with team members and apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market • Provide the technical leadership to the DV team for the project • Work independently on various DV tasks and provide technical guidance to the DV team. • Be involved technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup 【職務條件】 • Master’s degree in Electrical Engineering, Computer Science, or related. • Good understanding of ASIC design verification flow. • RTL coding with Verilog/System Verilog and familiar with front-end design flow and C/C++ programming experiences. • Knowledge of Perl, OVL, SVA, SV, UVM, OVM, script programming, etc. 【其他條件】 • MSEE with a minimum of 5 years, or BSEE with a minimum of 8 years of experience in digital ASIC/SOC design verification • MS/BS degree in EE or CS with expertise in digital IP/SOC design verification.

1. Participate in digital design specification, architecture definition, and microarchitecture planning. 2. Conduct FPGA prototyping, testing, and debugging of digital IP designs. 3. Collaborate closely with analog/mixed-signal design teams, firmware engineers, and system engineers to ensure successful product integration. 4. Develop, implement, and verify RTL code (Verilog/SystemVerilog) for high-speed Serdes interfaces including USB, DP, HDMI, DDR and PCIe.

1.Work with Hardware, BIOS ,BMC, and Firmware team for CPLD design, validation, and maintenance 2.Develop Server production power on sequence control logic by CPLD / FPGA 3.Implement new technology and design concept in CPLD / FPGA Design test plan, development specification, and issue tracking.

DRAM數位邏輯電路設計 『具工作經驗者，薪資另議』

The Staff/Sr. Engineer, CPLD will be based in Taiwan Taipei Wugu Site. The Staff/Sr. Engineer, CPLD performs the responsibility for CPLD programming and validation in Server/Storage Projects request. What a typical day looks like: 1. Skilled FPGA/CPLD Design Engineer with strong capabilities in Server/Storage system and hardware-level design. 2. Responsible for development and integration of CPLD/FPGA that implement functionality on prototypes: spanning from low-level hardware sequence control, logic control & status for embedded systems, to high-speed links, to high level IP blocks, to custom hardware-accelerated algorithms & filters. 3. Work closely with Hardware, BIOS, BMC and Firmware team for CPLD/FPGA development. 4. Designing validation plan and development spec. 5. Debugging platform and systems issues. The experience we are looking to add to our team: 1. 3-10 years of working experience in Firmware development. 2. Familiar in Verilog RTL language. Experienced with CPLD/FPGA development on Lattice, Altera and Xilinx devices. 3. Experience with I2C, SPI, LPC, UART, PCIe protocol design 4. Experience with verification methodologies, RTL and gate level simulations and debug. 5.Good problem-solving skills. The information we collect: We may collect personal information that you choose to submit to us through the Website or otherwise provide to us. This may include your contact details; information provided in online questionnaires, feedback forms, or applications for employment; and information you provide such as CV/Resume. We will use your information for legitimate business purposes such as responding to comments or queries or answering questions; progressing applications for employment; allowing you to choose to share web content with others or; where you represent one of our customers or suppliers, administering the business relationship with that customer or supplier.

1. 主動式電子掃描陣列 (相控陣列) 雷達系統之數位控制。 2. 熟悉Verilog與FPGA開發流程，了解High-Level Synthesis開發技術。 3. 具有實作數位訊號處理與數位架構設計於FPGA之經驗。

Responsibilities: • Develop integrated verification environment. • Verify designs with system verilog and system verilog assertion. • Build, maintain and upgrade testbenches and their components using UVM-based methods. • Check functional coverage and code coverage • Create controlled random testcases. Pre-debug and provide debug reports. • Scripting experience using scripting languages like Perl and Python.

請至 https://forms.gle/d4Q9xUcuwRMZ97VV6 投遞履歷，透過平台投遞不會給予回覆唷！ 【關於張量科技】 張量科技成立於 2019 年，專注於衛星的姿態判定與控制系統 (Attitude Determination and Control Sub-system, ADCS)，致力於提供客戶更輕、更小、更省電的解決方案，使客戶降低任務成本、提升衛星的商業價值。我們的定位是一太空業的 Design & Test house，主攻衛星相關產品的研發、設計、試組裝、校正與測試。目前，公司的客戶與合作夥伴包括了美國、歐洲與亞州的民間企業與研究機構。 【為什麼你該選擇 張量科技】 除了基本勞基法保障內容，我們還提供 - 彈性上班：彈性上下班制度，上班不趕車、不用人擠人。 - 遠端工作：依據職位提供部分遠端工作。 - 分享活動：每月定期舉辦學術交流會議。 - 週休二日：免補班。(優於勞基法) - 身體健康檢查補助 【工作內容】 - 球型馬達驅動器開發與維護 - 馬達測試平台開發與維護 - 英文技術文件撰寫 【應備條件】 - 熟悉FOC理論及實作 - 使用MCU/DSP/FPGA驅動PMSM經驗 - 熟悉版本控制工具 - 具備馬達應用系統(如運動平台、自走車、機械手臂等)之運動控制設計經驗尤佳 【加分條件】 - 使用FPGA驅動馬達的經驗 - 參與衛星相關專案經驗 - 熟悉DSP、數位控制系統 - 熟悉馬達驅動電路

1. USB3.0 host/device開發驗證相關工作 2. RTL coding/synthesis/simulation/verification

* 擔任 Tech Lead 職務，帶領團隊建立所需技術，具備技術管理經驗 * 參與的技術有：Audio/Video/AI 以及 SOC DFT & Low power 相關 * 擔任 SOC Project Leader 職務，帶領團隊執行 SOC 計劃，具備專案管理經驗 * 參與的 SOC 產品有：車用晶片、Smart Audio、Edge AI 相關 * 參與產品與技術需求規格討論制定、架構設計規劃、與合作單位完成 IP/IC 設計

※ Job Contents: 1. DDR/HBM controller IP design 2. DDR/HBM IP customer support 3. Execute digital IP front-end flow ※ Requirements: 1. 3-years digital IC design experiences 2. Senior/Technical Manager: 8-years digital IC design experiences 3. Familiar with DDR protocol is a plus 4. Familiar with AMBA interface is a plus 5. Familiar with IC front-end design flow such as Lint/CDC, Synthesis, LEC/formality, PrimeTime STA is a plus

1. 熟Verilog及C/C++語言設計。 2. 規劃執行產品韌體之撰寫。 3. 執行、協助或配合韌體新技術之研發、導入。 4. 執行產品韌體測試。

Overview We are seeking a highly skilled FPGA Engineer to architect and implement high-performance digital logic for next-generation camera platforms. This role is pivotal in enabling real-time video processing and efficient sensor integration. Key Responsibilities Design & Implement Camera Interfaces: Develop FPGA logic to handle high-speed camera data streams (e.g., MIPI, LVDS, CSI). Real-Time Image Processing: Integrate or design FPGA IP cores for image signal processing, filtering, and feature extraction. Sensor Synchronization: Ensure precise timing between multiple camera modules and other sensor inputs. Latency Optimization: Optimize FPGA architectures for low-latency video capture and data throughput. Verification & Testing: Create simulation testbenches and perform hardware-in-the-loop testing for camera pipelines. Collaboration: Work closely with camera hardware and system integration teams to define requirements and validate performance.

我們正在尋找高速傳輸介面專家, 尤其擁有 USB 和 PCIe 技術的專業知識。理想的候選人應具有豐富的開發和優化 Windows 和 Linux 操作系統驅動程式的經驗。此職位需要與硬體和軟體團隊密切合作，以確保高速介面的無縫整合和性能。

1. 熟讀規格書，建立VPLAN 2. 使用SystemVerilog 程式語言設計，UVM 建立模擬環境 3. 執行CRT驗證流程 (使用使用VERDI VCS NC等工具) 4. 跨部門合作溝通 (設計&軟體等部門)

Be in charge of one of below items. 1. Digital IP coding (AMBA, Peripheral, MAC, Modem..) 2. SoC architecture define 3. MAC Layer protocol architecture define 4. Audio codec coding (I2S, SPDIF...) 5. Digital signal processing (Filter.. ) 6. IC design integration (top integration/synthesis/timing closure/DFT) Extra skill is plus. 1. Familiar with Zigbee, Bluetooth or WiFi system is plus. 2. Familiar with audio related processing is plus. 3. Familiar with Perl/Makefile/tcl is plus. 4. The passion to create a wonderful thing.

1.RTC Module/ IP design. 2.Design synthesis. 3.Design verification. 4.DFT/ siemens tools.