「Senior Digital Design Engineer」的相似工作

About us: VICI Holdings' Hardware team is seeking a skilled FPGA Engineer to join our dynamic group. In this role, you will be pivotal in advancing our trading systems, contributing to the development and enhancement of cutting-edge technologies. We boast the leading software development team in Taiwan and possess FPGA design technology in parallel with wall street trading firms. This expertise enables us to build low-latency, fully automated trading systems. Our trading strategies cover stocks, futures, and derivatives, achieving a daily global trading volume in the hundreds of millions dollars. Roles/ Responsibilities: • High speed IP interface design (such as PCIE gen 3, 4 / Ethernet, DDR etc.) • In charge of FPGA design/ implementation/simulation. • Transmission protocol layer development. • Optimizing hardware for latency. • Proficiency with Xilinx design environment. Candidate Requirements: • BS/MS degree above from EE, CE with 2+ years of relevant work experience • Experience in high-speed interface design or knowledge in PCIE/ Ethernet/MIPI/DDR design or implementation is a plus • Experience using System Verilog and at least two prior RTL design is a required. • Demonstrated ability to tackle complex design challenges and implement effective solutions Other Requirements: • High self-motivated individual with good communication skill. • English level – working level proficiency is a plus. Interview Process: • Resume selection ->Coding Test -> AI Interview (Online) -> F2F Interview -> HR Manager

The successful candidate will work with team members and apply his/her design techniques to work on different phases of complex logic design for ASIC/SOC project. The role will include working on the following tasks from time to time: HDL coding, documentation, RTL quality check, cooperate with back-end engineer etc. 【Key Responsibilities】 - Responsible for front-end digital logic design in ASIC/SOC projects. - Perform HDL coding (Verilog/SystemVerilog). - Prepare and maintain design documentation (specifications and design documents). - Conduct RTL quality checks (Lint, CDC, power analysis, etc.). - Collaborate with Backend/Physical Design engineers to achieve timing closure. 【Core Requirements】 - Education/Experience: Master’s degree with ≥ 2 years, or Bachelor’s degree with ≥ 3 years of digital ASIC/SOC design experience. - RTL Design: Proficient in RTL coding using Verilog/SystemVerilog or VHDL. - TO / Front-End Flow: Familiar with front-end design flow, including synthesis, Lint, CDC, and STA. - EDA Tools: Experience with tools such as Lint, CDC check, and PrimeTime PX (power analysis). - Documentation: Ability to write design specifications and technical documents. - Collaboration: Work closely with the Design Verification (DV) team on IP verification. 【Preferred Qualifications】 - Familiarity with CPU architectures (x86/ARM/8051). - Knowledge of AMBA bus protocols (AXI/AHB/APB). - Understanding of PCIe protocol.digital IP/SOC design verification.

Key responsibilities: • Perform IC design of FTDI products • Perform Verilog RTL design to meet product specifications and requirements • Perform front-end verification using UVM methodology • Work with Systems and Software engineers on FPGA verification • Perform Logic Synthesis, Static Timing Analysis • Lead DFT related activities - Scan Insertion, ATPG, Pattern Validation • Work with Physical designer to achieve timing closure • Work with test team in debugging production test issues • Help debug & correct any functional issues found in taped-out devices • Participate in design reviews, support ISO processes and documentation Additional responsibilities: a) Any reasonable task assigned by management and deemed to be within the individuals’ capabilities to ensure smooth running of the business. b) As this is an evolving business, ongoing change is an integral part of the position. Management will liaise with the individual on any fundamental change to work practices. The individual is required to embrace and adopt any change to working practices. Knowledge and skill requirements: • Degree/Master in Electrical/Electronic Engineering • 5 years or above experience in the area of digital IC design • Working experience from design to tape-out are essential • Experience in Verilog HDL and VHDL RTL design, OVM/UVM verification methodology , Logic Synthesis, DFT, ATPG, Timing Closure • Experience in using EDA tools from Cadence, Synopsys • Knowledge and working experience in one or more of the following: o Digital and mixed-signal design o USB interface products o Knowledge in connectivity technology such as USB, UART, SPI, I2C o Project Management Working conditions:  Working conditions are normal for an office environment.  Work requires willingness to work a flexible schedule.

【工作內容】 • Work with team members and apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market • Provide the technical leadership to the DV team for the project • Work independently on various DV tasks and provide technical guidance to the DV team. • Be involved technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup 【職務條件】 • Master’s degree in Electrical Engineering, Computer Science, or related. • Good understanding of ASIC design verification flow. • RTL coding with Verilog/System Verilog and familiar with front-end design flow and C/C++ programming experiences. • Knowledge of Perl, OVL, SVA, SV, UVM, OVM, script programming, etc. 【其他條件】 • MSEE with a minimum of 5 years, or BSEE with a minimum of 8 years of experience in digital ASIC/SOC design verification • MS/BS degree in EE or CS with expertise in digital IP/SOC design verification.

【About us】 VICI Holdings is a leading high-frequency trading company, and we are seeking talented and detail-oriented professionals to join our technology team. As a C++ Software Engineer in our trading group, you will play a crucial role in implementing trading strategies in the market. Ideal candidates should excel in C++ multithreading optimization, be adept at efficiently utilizing CPU and memory resources to achieve better latency, and have a strong understanding of Network Programming and network principles (experience with DPDK or other network card accelerations is a plus). The role requires implementing trading algorithms with minimal latency. If you are passionate about programming optimization, eager to learn cutting-edge techniques, and find great satisfaction in reducing program and trading system latency, this position is a perfect fit for you. 【Roles/ Responsibilities】 • Collaborate closely with traders and the hardware team to integrate and optimize quantitative algorithms within a low-latency fully automated trading system, and conduct testing and validation. • Develop back-testing platforms to meet strategy requirements. • Test and analyze latency data of the trading system, identify issues and bottlenecks, and continuously enhance the operational efficiency of the trading system. • Stay abreast of technological advancements and continuously refine the low-latency fully automated trading system. 【Candidate Requirements】 • Master’s degree in CS, EE, CE or a related technical field. • Proficient in Modern C++. • Expertise in C++ multithreading optimization. • Familiar with Network Programming and network operation principles (experience with kernel-bypass networking is highly desirable). • Knowledgeable in computer architecture with a focus on efficient utilization of hardware resources (experience with instruction-level optimizations such as SIMD is a plus). • Experienced in Linux system programming. 【Other Requirement】 • Strong technical documentation skills. • Highly self-motivated with excellent communication and cross-departmental collaboration abilities. • Experience in low-latency or high-frequency trading is a plus. • Familiarity with basic financial trading knowledge is a plus. th basic financial trading knowledge is a plus. • Experience in developing low-latency network card drivers or FPGA drivers is a plus. 【Interview Process】 The order may be adjusted depending on the situation. Resume selection -> Coding test -> AI Interview -> F2F Interview (Hiring Manager) VICI Holdings 威旭資訊是一間技術領先的高頻交易公司，我們正在尋找技術精湛、注重細節，且能與公司一起持續追求進步與成長的優秀人才，加入我們的技術團隊，一同打造領先全市場的低延遲全自動交易系統。 交易組的C++軟體工程師這個職位，扮演了將交易員策略具體實現在市場上的重要角色，理想的候選人需精通C++多執行緒優化，熟悉如何有效率的使用 CPU 與 memory 資源以達到更好的 latency，並了解 Network Programming與網路運作原理（具 DPDK 等網卡加速的經驗尤佳），理想的候選人將具備以最低延遲的實作方式實現交易員的量化演算法的能力。如果您對程式設計的優化充滿熱情，並對前沿優化技術具有一顆求知若渴的心，且能在逐步降低程式與交易系統延遲的工作過程中獲得巨大成就感，那麼這個職位將會非常適合您。 【工作職責】 ・與交易員、硬體部門緊密合作，將量化演算法與低延遲全自動交易系統進行整合與優化，並進行測試與驗證 ・協助交易員針對策略需求，建立回測平台 ・測試與分析交易系統延遲數據，排除問題並找出瓶頸，以不斷提升交易系統的運行效率 ・持續關注技術新知，不斷精進低延遲全自動交易系統 【專業能力需求】 ・資訊工程科系大學畢業或同等的電腦科學基礎 ・熟悉 Modern C++，並精通C++多執行緒優化 ・熟悉Network Programming與網路運作原理（熟悉 kernel-bypass networking者尤佳） ・熟悉計算機結構，了解如何有效率的運用計算機的硬體資源（具 SIMD 等instruction-level optimization相關經驗者尤佳） ・熟悉 Linux 系統程式設計 【其他需求】 ．具備良好的技術文書撰寫能力 ．高度推進自我要求，並具有良好的溝通與跨部門合作能力 ．有低延遲或高頻交易背景的經驗佳 (加分) ．熟悉基本金融交易知識佳 (加分) ．具低延遲網卡或 FPGA driver 開發經驗者佳 (加分) 【面試流程】可能視情況調整流程順序 履歷篩選 --> Coding Test --> 線上AI面試 --> 現場考題 ＆現場面試 --> HR面試

1. Participate in digital design specification, architecture definition, and microarchitecture planning. 2. Conduct FPGA prototyping, testing, and debugging of digital IP designs. 3. Collaborate closely with analog/mixed-signal design teams, firmware engineers, and system engineers to ensure successful product integration. 4. Develop, implement, and verify RTL code (Verilog/SystemVerilog) for high-speed Serdes interfaces including USB, DP, HDMI, DDR and PCIe.

我們正在尋找一位資深人員，帶領FPGA專案開發，包含主機板時序控制、客戶FPGA專案需求開發設計，及FPGA實作上必要時需與軟硬體研發團隊成員進行協作。 工作內容： 1. 數位邏輯設計並熟悉RTL Coding架構。 2. 熟悉並使用Altera Quartus或Xilinx Vivado開發FPGA系統。 3. 熟悉主機板CPU power sequence control。 4. 熟悉影像方面的高速介面(SDI/HDMI)、DDR高速介面、PCIe、I2C、UART、SPI等介面應用。 5. SoC FPGA系統整合。 6. FPGA IP 整合及驅動程式開發。

About us: VICI Holdings’ Quantitative team is seeking a Quantitative Researcher to integrate knowledge from statistics, information science, and finance to enhance our research capabilities. This role involves applying and learning diverse disciplines such as market microstructure, statistics, and machine learning. “Career Path”: As you achieve research milestones, there will be opportunities to pursue a career in high-frequency trader or quantitative trader, allowing you to develop automated trading strategies and further contribute to our innovative trading solutions. Roles/ Responsibilities: • End-to-end research and development, including idea generation, data processing, strategy back-testing, optimization, and production implementation. • Quantitative Model Development: Building model prototypes and conducting back-testing. • Conduct quantitative research independently including market data analysis, prototyping, strategy parameters tuning, and performance monitoring. • AI Algorithm trading strategy research. Candidate Requirements: • Degree in EE, CS, Mathematics, Physics, Statistics or related experience. • Programming skill in Python is a must. • Proficient in researching AI algorithm trading strategies is a plus. • Basic knowledge of finance and trading rules are a plus. • Familiarity with programming skills in C++ or R is a plus. Other Requirements: • High self-motivated individual with good communication skill. • Strong analytical and quantitative skills are a must. Interview Process: Resume selection -> Take home assessment -> AI Interview ->F2F assessment & Hiring Manager assessment (or Google meet) -> HR Manager VICI Holdings 威旭資訊是一間專注於高頻交易、造市及套利交易的公司，我們進行量化研究並追求更好的交易策略。擁有領先全台的軟體研發團隊，並具備華爾街等級的FPGA設計技術，據此打造低延遲全自動交易系統；同時，交易策略橫跨股票、期貨及衍生性商品，且每日全球交易市值達數百億台幣。 其中，計量研究人員是結合統計、資訊和財金的一份職務，在整個計量研究的期間將會同時使用及學習到不同領域的知識並將其結合，以上不同領域知識包含(但不僅限於)市場微結構、統計、機器學習(Machine Learning)。 為了使工作順利，需大量利用程式工具來完成任務，因此需俱備Python、R或C++等程式語言的基本使用能力。在累積一定的研究成果後，也有機會依個人意願發展高頻交易、量化交易員職涯，建立自動交易策略。 【工作內容】 ・金融數據分析（方法挑選、資料蒐集與分析）。 ・計量模型研發（建立模型原型、回測）。 ・AI演算法交易策略研究。 【能力需求】 ・電機、資工、生醫、數學、物理等理工相關科系。 ・對交易策略研究有強大的熱情。 ・熟悉Python（必要）、機器學習（必要） 【加分項】 ・具備基礎的金融相關知識與交易規則。 ・熟悉C++或任ㄧ程式語言。 【面試流程】可能視情況調整流程順序 履歷篩選 --> take home assessment --> 線上AI面試 -->現場考題 & 主管面試 （面試可選擇現場或是google meet）--> HR 面談 【投遞注意事項】 投遞請附上歷年成績單，包含大學及研究所（如有）及過往研究成果，形式可為論文、專題研究或是github連結。無法附件在104可以寄到[email protected]信箱。

1. SOC/IP 整合工作，從RTL到 Netlist 2. clock tree structure design 3. Lint / CDC check / Synthesis/ DFT/ LEC

1. Verilog or VHDL程式經驗 2. 應用FPGA之功能設計

1.數位IP相關功能的設計與實現 2.數位IP仿真與FPGA驗證 3.數位IP/subsys/chip_top的前段整合流程signoff 4.ISO 26262 FMEDA 設計和品質改進 5.與第三方數位 IP 供應商合作

1. USB4/USB3/DP/HDMI/PCIe or high speed serial IO controller development 2. IP integration and going with Design quality check flows (e.g. Lint/CDC/Synthesis/LEC …) 3. Familiar with Xilinx FPGA implementation flow for bit file generation 4. Experience in Xilinx FPGA GTY/GTM Transceivers Controlling is a plus 5. Familiar with Advanced Node Low Power Serial Link and IO/Network Architecture

1. 主動式電子掃描陣列 (相控陣列) 雷達系統之數位控制。 2. 熟悉Verilog與FPGA開發流程，了解High-Level Synthesis開發技術。 3. 具有實作數位訊號處理與數位架構設計於FPGA之經驗。

1. 具 0~2年數位晶片設計，或有 0~5年類比晶片設計工作經驗。 2. 具備基本數位和類比電路知識，熟習標準晶片設計流程。 3. 熟習業界常用EDA tools, 或Matlab/ Simulink。 4. 研習過CMOS or BiCMOS 類比設計電路課程，對放大器有基礎認識。 5. Experience in these areas is preferred： * BiCMOS or CMOS high-speed (>20Gb/s) circuit, Linear electrical amplifier & equalizer, High-speed (>25G) CDR/PLL/SerDes. * Linear optical laser driver & receiver (TIA + linear amplifier) 本職位負責類比IC電路的設計、驗證和除錯。這是一個高度技術性的職位，對公司的產品開發至關重要。我們正在尋找一位熱愛類比IC設計並具有相關經驗的人才，以推動公司的技術創新和發展。 如果您對這個職位感興趣，請投遞您的履歷表，我們立即與您聯繫。

我們專注於3D影像立體雙目視覺技術 產品應用於3D 影像辨識、360 度環景拍照、攝影或AR 與VR 職務內容： ★ USB2.0/3.1或 MIPI 介面之2D/ 3D 影像處理與壓縮之 IC 開發 ★ 影像處理與壓縮相關數位 IP暨產品之開發設計、測試、驗證 條件要求： 1. 對IP Verification, System Verification 有興趣 2. 熟Verilog coding 與 ASIC design Flow 與 Timing Closure 3. 或有 SoC IC 開發經驗 4. 對開發人工智慧((AI) 晶片與邊緣運算有興趣者

請至 https://forms.gle/d4Q9xUcuwRMZ97VV6 投遞履歷，透過平台投遞不會給予回覆唷！ 【關於張量科技】 張量科技成立於 2019 年，專注於衛星的姿態判定與控制系統 (Attitude Determination and Control Sub-system, ADCS)，致力於提供客戶更輕、更小、更省電的解決方案，使客戶降低任務成本、提升衛星的商業價值。我們的定位是一太空業的 Design & Test house，主攻衛星相關產品的研發、設計、試組裝、校正與測試。目前，公司的客戶與合作夥伴包括了美國、歐洲與亞州的民間企業與研究機構。 【為什麼你該選擇 張量科技】 除了基本勞基法保障內容，我們還提供 - 彈性上班：彈性上下班制度，上班不趕車、不用人擠人。 - 遠端工作：依據職位提供部分遠端工作。 - 分享活動：每月定期舉辦學術交流會議。 - 週休二日：免補班。(優於勞基法) - 身體健康檢查補助 【工作內容】 - 球型馬達驅動器開發與維護 - 馬達測試平台開發與維護 - 英文技術文件撰寫 【應備條件】 - 熟悉FOC理論及實作 - 使用MCU/DSP/FPGA驅動PMSM經驗 - 熟悉版本控制工具 - 具備馬達應用系統(如運動平台、自走車、機械手臂等)之運動控制設計經驗尤佳 【加分條件】 - 使用FPGA驅動馬達的經驗 - 參與衛星相關專案經驗 - 熟悉DSP、數位控制系統 - 熟悉馬達驅動電路

1. 負責數位IC設計整合: a. 依客戶需求設計整合IC功能、工作頻率、介面規格、消耗功率等基本規格 b. 完成SoC系統架構設計，並依功能單元運作屬性區分區塊規格 c. 使用Verilog/VHDL編程內部功能並撰寫RTL code 2. 負責功能驗證與除錯 a. 制定功能驗證計畫 b. 審核驗證計畫的完整性和正確性 c. 進行基本模擬，確認RTL code的功能 d. RTL code寫入FPGA晶片連接系統測試，驗證RTL code 3. 負責時序分析與功耗管理 a. 產出邏輯閘級電路連線網表(netlist) b. 進行SoC系統的時序分析 c. 進行SoC系統的功耗分析 4. 其它主管交辦事項 【必要條件】 1. 電機、電子、資訊工程或相關科系，碩士以上學歷 2. 三年以上 SoC 設計或整合經驗 3. 熟悉CPU子系統設計整合 a. 熟悉 ARM 架構， b. 對 RISC-V 架構有基本認識 4. 熟悉數位IC前端設計流程，如RTL design、Lint/CDC、Synthesis、STA、LEC、ECO等 5. 具類比IP整合相關經驗，例如PHY、Serdes、PLL等 6. 熟悉IC後段設計流程，如DFT、MBIST、P&R、post-cilicon system level debugging等

* 擔任 Tech Lead 職務，帶領團隊建立所需技術，具備技術管理經驗 * 參與的技術有：Audio/Video/AI 以及 SOC DFT & Low power 相關 * 擔任 SOC Project Leader 職務，帶領團隊執行 SOC 計劃，具備專案管理經驗 * 參與的 SOC 產品有：車用晶片、Smart Audio、Edge AI 相關 * 參與產品與技術需求規格討論制定、架構設計規劃、與合作單位完成 IP/IC 設計

Responsibilities: • Develop integrated verification environment. • Verify designs with system verilog and system verilog assertion. • Build, maintain and upgrade testbenches and their components using UVM-based methods. • Check functional coverage and code coverage • Create controlled random testcases. Pre-debug and provide debug reports. • Scripting experience using scripting languages like Perl and Python.

※ Job Contents: 1. DDR/HBM controller IP design 2. DDR/HBM IP customer support 3. Execute digital IP front-end flow ※ Requirements: 1. 3-years digital IC design experiences 2. Senior/Technical Manager: 8-years digital IC design experiences 3. Familiar with DDR protocol is a plus 4. Familiar with AMBA interface is a plus 5. Familiar with IC front-end design flow such as Lint/CDC, Synthesis, LEC/formality, PrimeTime STA is a plus