「Senior Digital Design Engineer」的相似工作

About us: VICI Holdings' Hardware team is seeking a skilled FPGA Engineer to join our dynamic group. In this role, you will be pivotal in advancing our trading systems, contributing to the development and enhancement of cutting-edge technologies. We boast the leading software development team in Taiwan and possess FPGA design technology in parallel with wall street trading firms. This expertise enables us to build low-latency, fully automated trading systems. Our trading strategies cover stocks, futures, and derivatives, achieving a daily global trading volume in the hundreds of millions dollars. Roles/ Responsibilities: • High speed IP interface design (such as PCIE gen 3, 4 / Ethernet, DDR etc.) • In charge of FPGA design/ implementation/simulation. • Transmission protocol layer development. • Optimizing hardware for latency. • Proficiency with Xilinx design environment. Candidate Requirements: • BS/MS degree above from EE, CE with 2+ years of relevant work experience • Experience in high-speed interface design or knowledge in PCIE/ Ethernet/MIPI/DDR design or implementation is a plus • Experience using System Verilog and at least two prior RTL design is a required. • Demonstrated ability to tackle complex design challenges and implement effective solutions Other Requirements: • High self-motivated individual with good communication skill. • English level – working level proficiency is a plus. Interview Process: • Resume selection ->Coding Test -> AI Interview (Online) -> F2F Interview -> HR Manager

The successful candidate will work with team members and apply his/her design techniques to work on different phases of complex logic design for ASIC/SOC project. The role will include working on the following tasks from time to time: HDL coding, documentation, RTL quality check, cooperate with back-end engineer etc. 【Key Responsibilities】 - Responsible for front-end digital logic design in ASIC/SOC projects. - Perform HDL coding (Verilog/SystemVerilog). - Prepare and maintain design documentation (specifications and design documents). - Conduct RTL quality checks (Lint, CDC, power analysis, etc.). - Collaborate with Backend/Physical Design engineers to achieve timing closure. 【Core Requirements】 - Education/Experience: Master’s degree with ≥ 2 years, or Bachelor’s degree with ≥ 3 years of digital ASIC/SOC design experience. - RTL Design: Proficient in RTL coding using Verilog/SystemVerilog or VHDL. - TO / Front-End Flow: Familiar with front-end design flow, including synthesis, Lint, CDC, and STA. - EDA Tools: Experience with tools such as Lint, CDC check, and PrimeTime PX (power analysis). - Documentation: Ability to write design specifications and technical documents. - Collaboration: Work closely with the Design Verification (DV) team on IP verification. 【Preferred Qualifications】 - Familiarity with CPU architectures (x86/ARM/8051). - Knowledge of AMBA bus protocols (AXI/AHB/APB). - Understanding of PCIe protocol.digital IP/SOC design verification.

我們正在尋找一位資深人員，帶領FPGA專案開發，包含主機板時序控制、客戶FPGA專案需求開發設計，及FPGA實作上必要時需與軟硬體研發團隊成員進行協作。 工作內容： 1. 數位邏輯設計並熟悉RTL Coding架構。 2. 熟悉並使用Altera Quartus或Xilinx Vivado開發FPGA系統。 3. 熟悉主機板CPU power sequence control。 4. 熟悉影像方面的高速介面(SDI/HDMI)、DDR高速介面、PCIe、I2C、UART、SPI等介面應用。 5. SoC FPGA系統整合。 6. FPGA IP 整合及驅動程式開發。

The Staff/Sr. Engineer, CPLD will be based in Taiwan Taipei Wugu Site. The Staff/Sr. Engineer, CPLD performs the responsibility for CPLD programming and validation in Server/Storage Projects request. What a typical day looks like: 1. Skilled FPGA/CPLD Design Engineer with strong capabilities in Server/Storage system and hardware-level design. 2. Responsible for development and integration of CPLD/FPGA that implement functionality on prototypes: spanning from low-level hardware sequence control, logic control & status for embedded systems, to high-speed links, to high level IP blocks, to custom hardware-accelerated algorithms & filters. 3. Work closely with Hardware, BIOS, BMC and Firmware team for CPLD/FPGA development. 4. Designing validation plan and development spec. 5. Debugging platform and systems issues. The experience we are looking to add to our team: 1. 3-10 years of working experience in Firmware development. 2. Familiar in Verilog RTL language. Experienced with CPLD/FPGA development on Lattice, Altera and Xilinx devices. 3. Experience with I2C, SPI, LPC, UART, PCIe protocol design 4. Experience with verification methodologies, RTL and gate level simulations and debug. 5.Good problem-solving skills. The information we collect: We may collect personal information that you choose to submit to us through the Website or otherwise provide to us. This may include your contact details; information provided in online questionnaires, feedback forms, or applications for employment; and information you provide such as CV/Resume. We will use your information for legitimate business purposes such as responding to comments or queries or answering questions; progressing applications for employment; allowing you to choose to share web content with others or; where you represent one of our customers or suppliers, administering the business relationship with that customer or supplier.

【About us】 VICI Holdings is a leading high-frequency trading company, and we are seeking talented and detail-oriented professionals to join our technology team. As a C++ Software Engineer in our trading group, you will play a crucial role in implementing trading strategies in the market. Ideal candidates should excel in C++ multithreading optimization, be adept at efficiently utilizing CPU and memory resources to achieve better latency, and have a strong understanding of Network Programming and network principles (experience with DPDK or other network card accelerations is a plus). The role requires implementing trading algorithms with minimal latency. If you are passionate about programming optimization, eager to learn cutting-edge techniques, and find great satisfaction in reducing program and trading system latency, this position is a perfect fit for you. 【Roles/ Responsibilities】 • Collaborate closely with traders and the hardware team to integrate and optimize quantitative algorithms within a low-latency fully automated trading system, and conduct testing and validation. • Develop back-testing platforms to meet strategy requirements. • Test and analyze latency data of the trading system, identify issues and bottlenecks, and continuously enhance the operational efficiency of the trading system. • Stay abreast of technological advancements and continuously refine the low-latency fully automated trading system. 【Candidate Requirements】 • Master’s degree in CS, EE, CE or a related technical field. • Proficient in Modern C++. • Expertise in C++ multithreading optimization. • Familiar with Network Programming and network operation principles (experience with kernel-bypass networking is highly desirable). • Knowledgeable in computer architecture with a focus on efficient utilization of hardware resources (experience with instruction-level optimizations such as SIMD is a plus). • Experienced in Linux system programming. 【Other Requirement】 • Strong technical documentation skills. • Highly self-motivated with excellent communication and cross-departmental collaboration abilities. • Experience in low-latency or high-frequency trading is a plus. • Familiarity with basic financial trading knowledge is a plus. th basic financial trading knowledge is a plus. • Experience in developing low-latency network card drivers or FPGA drivers is a plus. 【Interview Process】 The order may be adjusted depending on the situation. Resume selection -> Coding test -> AI Interview -> F2F Interview (Hiring Manager) VICI Holdings 威旭資訊是一間技術領先的高頻交易公司，我們正在尋找技術精湛、注重細節，且能與公司一起持續追求進步與成長的優秀人才，加入我們的技術團隊，一同打造領先全市場的低延遲全自動交易系統。 交易組的C++軟體工程師這個職位，扮演了將交易員策略具體實現在市場上的重要角色，理想的候選人需精通C++多執行緒優化，熟悉如何有效率的使用 CPU 與 memory 資源以達到更好的 latency，並了解 Network Programming與網路運作原理（具 DPDK 等網卡加速的經驗尤佳），理想的候選人將具備以最低延遲的實作方式實現交易員的量化演算法的能力。如果您對程式設計的優化充滿熱情，並對前沿優化技術具有一顆求知若渴的心，且能在逐步降低程式與交易系統延遲的工作過程中獲得巨大成就感，那麼這個職位將會非常適合您。 【工作職責】 ・與交易員、硬體部門緊密合作，將量化演算法與低延遲全自動交易系統進行整合與優化，並進行測試與驗證 ・協助交易員針對策略需求，建立回測平台 ・測試與分析交易系統延遲數據，排除問題並找出瓶頸，以不斷提升交易系統的運行效率 ・持續關注技術新知，不斷精進低延遲全自動交易系統 【專業能力需求】 ・資訊工程科系大學畢業或同等的電腦科學基礎 ・熟悉 Modern C++，並精通C++多執行緒優化 ・熟悉Network Programming與網路運作原理（熟悉 kernel-bypass networking者尤佳） ・熟悉計算機結構，了解如何有效率的運用計算機的硬體資源（具 SIMD 等instruction-level optimization相關經驗者尤佳） ・熟悉 Linux 系統程式設計 【其他需求】 ．具備良好的技術文書撰寫能力 ．高度推進自我要求，並具有良好的溝通與跨部門合作能力 ．有低延遲或高頻交易背景的經驗佳 (加分) ．熟悉基本金融交易知識佳 (加分) ．具低延遲網卡或 FPGA driver 開發經驗者佳 (加分) 【面試流程】可能視情況調整流程順序 履歷篩選 --> Coding Test --> 線上AI面試 --> 現場考題 ＆現場面試 --> HR面試

1. Participate in digital design specification, architecture definition, and microarchitecture planning. 2. Conduct FPGA prototyping, testing, and debugging of digital IP designs. 3. Collaborate closely with analog/mixed-signal design teams, firmware engineers, and system engineers to ensure successful product integration. 4. Develop, implement, and verify RTL code (Verilog/SystemVerilog) for high-speed Serdes interfaces including USB, DP, HDMI, DDR and PCIe.

ASIC design engineer responsible for post-RTL design flow. He/She will be responsible for block and /or chip level synthesis, timing closure, DFT generation, and ECOs. The responsibilities include but are not limited to. •    Improve the design methodology and flow. •    Synthesis, timing closure, and DFT support for various types of SerDes IPs ranging from 10Gbps to 224Gbps data rates for different applications. •    Collaborate with Analog/Digital design teams to deliver competitive SerDes IP solutions for all the Marvell product lines. •    Provide support to the product teams, for both pre and post-silicon

【工作內容】 • Work with team members and apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market • Provide the technical leadership to the DV team for the project • Work independently on various DV tasks and provide technical guidance to the DV team. • Be involved technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup 【職務條件】 • Master’s degree in Electrical Engineering, Computer Science, or related. • Good understanding of ASIC design verification flow. • RTL coding with Verilog/System Verilog and familiar with front-end design flow and C/C++ programming experiences. • Knowledge of Perl, OVL, SVA, SV, UVM, OVM, script programming, etc. 【其他條件】 • MSEE with a minimum of 5 years, or BSEE with a minimum of 8 years of experience in digital ASIC/SOC design verification • MS/BS degree in EE or CS with expertise in digital IP/SOC design verification.

1. 主FPGA與CPLD專案開發與維護 2. 熟RTL coding, 具Xilinx ISE/Vivado或Altera Quartus II專案設計經驗 3. 能與軟,韌,硬體等相關部門co-work 4. 具Xilinx PCIe 與 MIG DDR3/4系統整合經驗者佳

1.Work with Hardware, BIOS ,BMC, and Firmware team for CPLD design, validation, and maintenance 2.Develop Server production power on sequence control logic by CPLD / FPGA 3.Implement new technology and design concept in CPLD / FPGA Design test plan, development specification, and issue tracking.

DRAM數位邏輯電路設計 『具工作經驗者，薪資另議』

我們專注於3D影像立體雙目視覺技術 產品應用於3D 影像辨識、360 度環景拍照、攝影或AR 與VR 職務內容： ★ USB2.0/3.1或 MIPI 介面之2D/ 3D 影像處理與壓縮之 IC 開發 ★ 影像處理與壓縮相關數位 IP暨產品之開發設計、測試、驗證 條件要求： 1. 對IP Verification, System Verification 有興趣 2. 熟Verilog coding 與 ASIC design Flow 與 Timing Closure 3. 或有 SoC IC 開發經驗 4. 對開發人工智慧((AI) 晶片與邊緣運算有興趣者

Overview We are seeking a highly skilled FPGA Engineer to architect and implement high-performance digital logic for next-generation camera platforms. This role is pivotal in enabling real-time video processing and efficient sensor integration. Key Responsibilities Design & Implement Camera Interfaces: Develop FPGA logic to handle high-speed camera data streams (e.g., MIPI, LVDS, CSI). Real-Time Image Processing: Integrate or design FPGA IP cores for image signal processing, filtering, and feature extraction. Sensor Synchronization: Ensure precise timing between multiple camera modules and other sensor inputs. Latency Optimization: Optimize FPGA architectures for low-latency video capture and data throughput. Verification & Testing: Create simulation testbenches and perform hardware-in-the-loop testing for camera pipelines. Collaboration: Work closely with camera hardware and system integration teams to define requirements and validate performance.

1. IC產品之研發與應用設計 2. 建立IC產品基礎規格並設計IC電路 3. 降低產品成本，提高IC品質，支援軟/硬體開發 4. 熟數位IC設計及相關工具 Verilog HDL、Cadence IES simulator 、FPGA tools、Synopsys DC

1.RTC Module/ IP design. 2.Design synthesis. 3.Design verification. 4.DFT/ siemens tools.

* 擔任 Tech Lead 職務，帶領團隊建立所需技術，具備技術管理經驗 * 參與的技術有：Audio/Video/AI 以及 SOC DFT & Low power 相關 * 擔任 SOC Project Leader 職務，帶領團隊執行 SOC 計劃，具備專案管理經驗 * 參與的 SOC 產品有：車用晶片、Smart Audio、Edge AI 相關 * 參與產品與技術需求規格討論制定、架構設計規劃、與合作單位完成 IP/IC 設計

1. 具 0~2年數位晶片設計，或有 0~5年類比晶片設計工作經驗。 2. 具備基本數位和類比電路知識，熟習標準晶片設計流程。 3. 熟習業界常用EDA tools, 或Matlab/ Simulink。 4. 研習過CMOS or BiCMOS 類比設計電路課程，對放大器有基礎認識。 5. Experience in these areas is preferred： * BiCMOS or CMOS high-speed (>20Gb/s) circuit, Linear electrical amplifier & equalizer, High-speed (>25G) CDR/PLL/SerDes. * Linear optical laser driver & receiver (TIA + linear amplifier) 本職位負責類比IC電路的設計、驗證和除錯。這是一個高度技術性的職位，對公司的產品開發至關重要。我們正在尋找一位熱愛類比IC設計並具有相關經驗的人才，以推動公司的技術創新和發展。 如果您對這個職位感興趣，請投遞您的履歷表，我們立即與您聯繫。

1. SOC/IP 整合工作，從RTL到 Netlist 2. clock tree structure design 3. Lint / CDC check / Synthesis/ DFT/ LEC

About Us: VICI Holdings' IT Team is looking for a proactive and reliable MIS Engineer to join our dynamic environment. In this role, you will be responsible for supporting daily IT operations and office infrastructure, maintaining server rooms and lab environments to ensure optimal system performance, and providing timely technical support to internal users across departments. This is a hands-on position that plays a critical role in ensuring operational continuity and IT service excellence. Roles/ Responsibilities: • Provide technical support and troubleshooting for office user issues. • Manage and operate server systems, including AD, DNS, NAS, storage, and general server infrastructure. • TAdminister and maintain Linux-based services. • Oversee server room operations and perform routine maintenance. • Conduct IT asset inventory and manage hardware/software resources. • Assist with ad hoc tasks and assignments from supervisors. Candidate Requirements: • Proficiency in Windows Active Directory architecture and administration • Hands-on experience with VMware management and maintenance • Familiarity with NAS and storage systems, including backup strategies • Understanding of basic cybersecurity configurations and best practices • Experience managing both Linux and Windows environments • Knowledge of server hardware assembly and configuration (e.g., Dell, SuperMicro, HP) Other Requirements: • Familiarity with VMware Horizon VDI infrastructure and virtual desktop environments. • Experience working with Intel and AMD x86 architecture products • Hands-on experience in PC assembly and performance tuning, including overclocking. • Proactive mindset with a focus on continuously optimizing workflows and IT services. Interview Process: (The interview process may be adjusted based on specific circumstances) • Phone Interview(HR) -> F2F Interview(Hiring Manager) + On-Site Test -> HR

【工作內容】 1. 數位電路邏輯控制程式設計 2. 基本通訊界面控制 (UART/I2C/SPGIO/SPI) 3. CPLD規格評估 4. CPLD規格書規劃、撰寫、維護 5. Verilog/VHDL模擬除錯設計 6. CPLD測試、除錯、驗證及最佳化 7. 維護現有CPLD專案 【其他條件&加分項目】 1. 熟悉 Verilog, 2. 若具有 Altera Quartus II, Lattice Diamond , Modelsim能力佳 3. 具有開創性及解決問題的能力 4. 客戶導向及良好溝通技巧 5. 具備推動團隊完成任務的能力 6. 流程管理能力