「Sr. APR Engineer(台北)」的相似工作

1.Develop validation plans, execute system-level qualification tasks, and conduct stress tests to evaluate product reliability. 2.Support compatibility testing for PD, HUB, and related products. 3.Analyze root causes and provide relevant debugging information to assist R&D in resolving issues. 4.Summarize qualification results and compile the final QA report. 5.Support the marketing and FAE team in analyzing field failures and provide feasible solutions based on findings.

1. Support customer projects from design-in, design-through to mass-production. 2. Team work with AE, FAE, RD and QA to solve problems.

1. 負責後段APR flow 　 Familiar Netlist-to-GDS Design flow. Including,Floorplan/Power Plan/IR drop analysis、Placement/CTS/Route、Timing Analysis . 2. Physical Verification. Including, -DRC/LVS to tapeout. 3. 負責與客戶做設計服務的技術討論 4. 作為Project leader與APR團隊合作完成專案 5. 對IP survey有一定程度的了解為佳

DESCRIPTION: 1. Responsible for the physical design process of chip numbers from netlist to GDSII 2. Responsible for interaction with the front-end design team to realize the design convergence and optimization of the front and back ends; Comprehensive, static timing analysis 3. Floor planning, power planning and signoff, place and route, timing closure, chip static timing analysis and physical verification 4. IP integration, synthesis, verification and correction 5. Other Assigned Tasks delivered by the Line Manager QUALIFICATIONS: 1. MS degree in EE or related. 2. Familiar with physical design flow, including hierarchical design and low power design is a plus 3. Familiar with EDA tools, such as SoC Encounter/INNOVUS/ICC/ICC2 is a plus 4. Familiar with computer languages such as Perl/TCL/C-shell 5. Self-motivated with good communication skills and team spirit 6. Ability to understand and articulate technical issues. 7. Fluent English is a plus. 8. Experience in 12/5nm design is a plus.

1.Support Design Engineer on Signal Integrity testing and Debugging on Chip and Demo Board 2.Support Customer projects design-in stage to mass-production. 3.Support Customer projects design review (Schematics, layout, CTS report) 4.Team work with RD, AE and QA on debugging and problems solve.

Please apply this role through https://careers.synopsys.com/job/hsinchu/r-and-d-engineering-sr-staff-engineer/44408/84900058096 Synopsys is looking for motivated Product Engineer to help design, develop and test state of the art Static Timing, Characterization and Library modelling tools. The primary focus of the Product Engineer is closely working with R&D team, to influence technologies/solution roadmaps and provide R&D team with accurate input from Field AEs, helping them focus on the most critical design challenges and help define solutions to critical problems. The engineer will work closely with Field AEs, ensuring overall consistency of end-to-end design and analysis flow to meet customer needs. The engineer will also work with Sales and Marketing teams to find and develop new markets, drive new tool evaluations and help customers with the adoption and continuous usage of Static Timing, Characterization and Library Modelling, thus enabling Chip Design customers achieve best Timing, Power and Characterization Goals. Synopsys’ existing and forthcoming tools offer an advanced transistor-level static timing characterization and library modelling solution that addresses the existing and emerging challenges in custom and memory design. They offer predictability and improved productivity to designers. Their concurrent timing, SI features and advanced variation aware analysis enables designers to accurately and quickly identify design issues early-on and avoid expensive late-finding of problems in silicon. Main responsibilities: • Drive new products and new product features that exceed customer needs. • Work with RnD to enable timely implementation of new products and features, and important bug fixes. • Provide consultation to prospective users and/or product capability assessment and validation. • Provide tool trainings to customers and Field AEs. • Provides technical expertise to sales staff through sales presentations and product demonstrations. • Assists the sales staff in assessing potential application of company products to meet customer needs and preparing detailed product specifications for the development and implementation of customer applications/solutions. Requirements: We are looking for an innovative, motivated, and dependable person, with at least BS degree and 8+ years of recent hands-on experience including: · Exceptional expertise in transistor-level analysis and debug circuit level issues for SRAM, RF, ROM memories and Standard Cells. · Good exposure to static timing concepts and CMOS engineering fundamentals. · Good knowledge of TCL and or other scripting languages. · Very good communication, social and leadership skills. Plus: · NanoTime or PrimeLib experience highly desirable.

The successful candidate will work with team members and apply his/her design techniques to work on different phases of complex logic design for ASIC/SOC project. The role will include working on the following tasks from time to time: HDL coding, documentation, RTL quality check, cooperate with back-end engineer etc. 【Key Responsibilities】 - Responsible for front-end digital logic design in ASIC/SOC projects. - Perform HDL coding (Verilog/SystemVerilog). - Prepare and maintain design documentation (specifications and design documents). - Conduct RTL quality checks (Lint, CDC, power analysis, etc.). - Collaborate with Backend/Physical Design engineers to achieve timing closure. 【Core Requirements】 - Education/Experience: Master’s degree with ≥ 2 years, or Bachelor’s degree with ≥ 3 years of digital ASIC/SOC design experience. - RTL Design: Proficient in RTL coding using Verilog/SystemVerilog or VHDL. - TO / Front-End Flow: Familiar with front-end design flow, including synthesis, Lint, CDC, and STA. - EDA Tools: Experience with tools such as Lint, CDC check, and PrimeTime PX (power analysis). - Documentation: Ability to write design specifications and technical documents. - Collaboration: Work closely with the Design Verification (DV) team on IP verification. 【Preferred Qualifications】 - Familiarity with CPU architectures (x86/ARM/8051). - Knowledge of AMBA bus protocols (AXI/AHB/APB). - Understanding of PCIe protocol.digital IP/SOC design verification.

歡迎2026年畢業並正在找尋研發替代役的同學申請! 職位選擇: Direction 1: Physical Design Engineer Direction 2: ASIC Physical Design Engineer Direction 3: DFX Engineer Direction 4: CAD Tools Development Engineer Direction 5: Design Verification Engineer What you’ll be doing: Key Domains: • Physical and ASIC Design Implementation • Backend and Layout Optimization • Design-for-Excellence (DFX: Test, Manufacturability, Debug) • Development of CAD/EDA Automation Tools • Functional and Formal Design Verification What we need to see: • MS degree from EE/CS or related majors from a prestigious university. • Good knowledge in digital circuit design. • Experience in using Verilog HDL. • Experience in various EDA tools. • Fluent in English reading and writing. • Self-motivated, good team player. Ways to stand out from the crowd: • Proven ability to work independently as well as in a multi-disciplinary group environment • Good command of C/C++ or Verilog programming language. • Familiar with Perl/Python/Tcl/Shell scripting 應徵方式: 請提供以下資料： • 英文個人履歷 • 學士+碩士成績單 (中英文皆可) 提交申請: 請將上述資料投遞至104，符合資格者將會收到進一步的聯繫通知。

我們正在尋找具 2-3年以上經驗的資深版圖工程師，能獨立負責 Analog/Mixed-Signal/SoC IP 及 Top-Level Layout。 需熟悉 layout tool、CMOS 製程與 DRC/LVS 驗證，具高速介面經驗佳。 此職位需規劃 Floorplan、Power/Clock Routing、跨部門協作。 曾參與完整 Tape-out 專案者優先。 職務內容： 1.Interface IP layout 2.Ensure DRC/LVS clean 3.Ensure DRC/LVS clean 4.Fix EM/IR issue 5.Layout environment setup 6.IO planning, placement and routing 7.Help designer to debug and support FIB plan

1. 具 0~2年數位晶片設計，或有 0~5年類比晶片設計工作經驗。 2. 具備基本數位和類比電路知識，熟習標準晶片設計流程。 3. 熟習業界常用EDA tools, 或Matlab/ Simulink。 4. 研習過CMOS or BiCMOS 類比設計電路課程，對放大器有基礎認識。 5. Experience in these areas is preferred： * BiCMOS or CMOS high-speed (>20Gb/s) circuit, Linear electrical amplifier & equalizer, High-speed (>25G) CDR/PLL/SerDes. * Linear optical laser driver & receiver (TIA + linear amplifier) 本職位負責類比IC電路的設計、驗證和除錯。這是一個高度技術性的職位，對公司的產品開發至關重要。我們正在尋找一位熱愛類比IC設計並具有相關經驗的人才，以推動公司的技術創新和發展。 如果您對這個職位感興趣，請投遞您的履歷表，我們立即與您聯繫。

1. Participate in digital design specification, architecture definition, and microarchitecture planning. 2. Conduct FPGA prototyping, testing, and debugging of digital IP designs. 3. Collaborate closely with analog/mixed-signal design teams, firmware engineers, and system engineers to ensure successful product integration. 4. Develop, implement, and verify RTL code (Verilog/SystemVerilog) for high-speed Serdes interfaces including USB, DP, HDMI, DDR and PCIe.

Position Description: 1. To provide key technical support in digital IC design implementation, product demonstration, and sales presentations. 2. To demonstrate strong ability and to be hands-on in RTL-to-GDSII design methodology, including both challenging low power and high-performance designs. 3. Have real design experience including floorplan and partition, place, CTS, route, STA timing closure, Physical verification, RC extraction, Power Network analysis. 4. Assist in technical evaluation, assessment and delivery of concurrent ASIC/SoC designs. 5. To play a leading role among other team members, while receive little instruction on routine and general assignments. Position Requirements: 1. A bachelor's degree is essential and 3+ years’ experience in IC design, electronic engineering or computer science applications. 2. Ability to understand and articulate technical issues, (and knowledge of) design products and their applications. 3. Requires working knowledge of one or more programming languages, and effective communication and soft skills. 4. An MS degree and/or working experience in multi-nation IC design house/or familiar with EDI/Innovus product is a plus. 5. Good communication in English and good work attitude. 6. Be familiar with shell/Perl/Tcl etc. script language.

Responsible for developing custom IP for SoC design from specification definition, circuit design to testing, and familiar with component and process characteristics.

In this role you will: • Serve as the primary lawyer responsible for counseling the procurement organization and the business on a broad range of commercial and regulatory matters including structuring, drafting and negotiating commercial transactions • Serve as the primary Contract Management resource for Entegris’ APAC operations • You and the team will work directly with the sourcing team and the business. • You will serve as lead counsel on strategic deals • Provide day-to-day advice, resolve issues that arise in existing commercial relationships and handle pre-litigation legal disputes and inquiries • Principal duties include structuring, drafting and negotiating complex procurement agreements • Provide ongoing legal counseling in a wide range of legal areas • Systematically analyze complex problems, draw relevant conclusions and implement appropriate solutions. • Exhibit excellent negotiating and persuasive skills. • Participate in projects to improve the efficiency of the contract management process including implementing software platform updates/changes, contract data optimization and reviews to drive improvements. • Contribute to the continuous improvement of procurement contracts (minimizing risk, maximizing value) by updating contract templates, contract language and sharing of best practices • Play a key role in the Law Department and be a partner to the strategy, buyer and category management excellence teams.

1. 新產品開發管理 2. 專案開發管理 3. 新技術導入 4. 新產品開發投資效益分析，資訊評估

Responsibilities: • Develop integrated verification environment. • Verify designs with system verilog and system verilog assertion. • Build, maintain and upgrade testbenches and their components using UVM-based methods. • Check functional coverage and code coverage • Create controlled random testcases. Pre-debug and provide debug reports. • Scripting experience using scripting languages like Perl and Python.

負責 3D-IC Interposer 與類比 IP 佈局設計 (Virtuoso / Allegro)，確保電性與實體規格，優化設計流程。 熟悉 Layout tools、Foundry PDK為佳。

Job Description: In this position the individual will develop test environment, test plan, and test cases based on the product specification and related industrial standards. The individual will require initiating a test plan review with the team and updating the test plan accordingly. The candidate will require executing and developing the test cases based on test plan, debugging and reporting the test result to achieve full function coverage goal. The individual will require developing ASIC bench functional test programs and doing ASIC bring-up and ASIC bench testing. The ideal individual must have proven ability to achieve results in a fast moving, dynamic environment. The candidate must have ability to coordinate priorities and initiatives and clear communication skill.

1. 機櫃應用架構設計 2. RFQ Proposal & development 3. Project execution (WBS) 4. Technical development 5. 機構規格確認 6. 機構設計&確認 7. 跨部門溝通 8. 設計文件建立

1. 協助業務向客戶介紹產品應用與規格 2. 協助工廠PD/PE新產品生產 3. 瞭解業界趨勢，做新產品規劃與前期開發