1. Architecture design and RTL implementation of Automotive/Smartphone chipset
2. SoC system power and performance analysis
3. SoC system bus and memory subsystem design, integration, and modeling
4. SoC low power design, integration, and modeling
5. SoC functional safety analysis, design, integration, and modeling
6. SoC cyber security analysis, design, integration, and modeling
We are seeking a highly motivated Digital IC Design Engineer to join our dynamic team. The ideal candidate will have a strong background in digital design, a passion for innovation, and the ability to work collaboratively in a fast-paced environment.
1.Design and implement digital integrated circuits for low power MCU, including timing control, image processing, GPIO, and interface control.
2.Collaborate with cross-functional teams to define specifications and requirements.
3.Perform RTL design using VHDL/Verilog and simulation using tools such as ModelSim or VCS.
4.Conduct functional verification and validation of designs through simulation and formal methods.
5.Develop low power image processing and camera control algorithms, pipelines, and HW-friendly imaging technologies.
6.Hand on ISP block (AE, AWB, BPC, etc.) design and modification.
7.Optimize designs for performance, area, and power consumption.
8.Participate in design reviews and provide constructive feedback.
9.Assist in the integration and testing of digital systems.
10.Review technical literature, collect data, and specify solution options. Design, analyze, simulate, test, and document algorithm options.
11.Familiar with MIPI, I2C, serial, parallel output data control is plus.
12.Familiar with design flow and block integration is plus. (Required for manager)
13.Participate in system requirements definitions and schedule plan. ( Required for manager).
Preferred Qualifications:
1.Experience with low-power design techniques.
2.Knowledge of hardware description languages and electronic design automation (EDA) tools.
3.Familiarity with mixed-signal design concepts is a plus.
SOC-NxSOC(next generation) team is hiring both junior and senior engineers, whose work scope is implement methodology development and PPA optimization from RTL to GDS.
Join us, you will work together with expertise in all these areas; you will not only work for SOC development, but also enjoy and experience for all related products: smart phone/ tablet/ wearable/automotive etc.; you will work for the most advanced process/technology, the best chip in the world.
What you'll be doing:
- Methodology development at all stages, including synthesis, PnR, timing, IR, PV etc
- PPA optimization
What we need to see:
- BSEE, MSEE is preferred
- Project experience in IC design implementation
- Courses taken in circuit design, digital design
- Hand-on experience in EDA software from Synopsys (DC/FC-fe/FC-be/ICC2/PT/Formality),
Cadence (Innovus), Ansys(Redhawk/RHSC) is preferred
Ways to stand out from the crowd:
- Proficient user of Perl, Python or TCL is preferred
- Excellent English communication skill
【工作內容】
• Work with team members and apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market
• Provide the technical leadership to the DV team for the project
• Work independently on various DV tasks and provide technical guidance to the DV team.
• Be involved technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup
【職務條件】
• Master’s degree in Electrical Engineering, Computer Science, or related.
• Good understanding of ASIC design verification flow.
• RTL coding with Verilog/System Verilog and familiar with front-end design flow and C/C++ programming experiences.
• Knowledge of Perl, OVL, SVA, SV, UVM, OVM, script programming, etc.
【其他條件】
• MSEE with a minimum of 5 years, or BSEE with a minimum of 8 years of experience in digital ASIC/SOC design verification
• MS/BS degree in EE or CS with expertise in digital IP/SOC design verification.
【產品線描述】
1. AMOLED, AR, VR, TDDI等面板驅動IC與觸控IC設計
2. 頂級系統廠ASIC產品合作開發
【工作說明】
1. 高速介面設計
2. 記憶體控制單元設計
3. 面板時序電路設計
4. 面板顯示優化控制單元設計
【必要條件】
1. MS degree in EE fields
2. Good at digital IC front-end design flow such as Verilog RTL design, Synopsys Design compiler, LEC, PrimeTime STA and FPGA
3. Must be a good team player with strong desire to succeed.