「數位IC設計工程師2-11(新竹)」的相似工作

負責IP開發、整合與偵錯 -- 利用Verilog/SystemC從事邏輯設計與數位系統設計，以相關自動化軟體進行電路合成及模擬驗證，並配合利用FPGA系統平台進行系統整合與測試驗證。

1. Digital IP design and verification 2. SOC integration and verification

1. Architecture design and RTL implementation of Automotive/Smartphone chipset 2. SoC system power and performance analysis 3. SoC system bus and memory subsystem design, integration, and modeling 4. SoC low power design, integration, and modeling 5. SoC functional safety analysis, design, integration, and modeling 6. SoC cyber security analysis, design, integration, and modeling

1. Speech/LCD 相關 ASIC 設計開發 2. IC spec訂定討論 (含 analog IP spec) 3. 數位電路設計、整合及 Back-end flow 4. 跨部門 IC 驗證 5. 協助處理良率及客訴問題

【產品範疇】 LCD – Mobile TDDI/車載/平板/工控 【工作內容】 1.Verilog RTL電路的設計與驗證 2.Chip及 IP 整合, DFT 及 Cad Tools 設計流程及驗證 3.CP/FT測試規劃及產出test pattern 【需求條件】 1. MS or PhD degree in EE, or relevant fields 2. 熟悉Verilog HDL, IC Design CAD Tools（simulation, synthesis, LEC, STA, etc.） 3. Whole-chip整合、邏輯電路設計及相關IC設計流程

1. 具有數位電路設計以及RTL coding基礎者 2. 熟悉EDA tool 3. 驅動IC相關經驗者優先

SOC-NxSOC(next generation) team is hiring both junior and senior engineers, whose work scope is implement methodology development and PPA optimization from RTL to GDS. Join us, you will work together with expertise in all these areas; you will not only work for SOC development, but also enjoy and experience for all related products: smart phone/ tablet/ wearable/automotive etc.; you will work for the most advanced process/technology, the best chip in the world. What you'll be doing: - Methodology development at all stages, including synthesis, PnR, timing, IR, PV etc - PPA optimization What we need to see: - BSEE, MSEE is preferred - Project experience in IC design implementation - Courses taken in circuit design, digital design - Hand-on experience in EDA software from Synopsys (DC/FC-fe/FC-be/ICC2/PT/Formality), Cadence (Innovus), Ansys(Redhawk/RHSC) is preferred Ways to stand out from the crowd: - Proficient user of Perl, Python or TCL is preferred - Excellent English communication skill

1. BT Control Layer 2. BLE Link Layer Development and Maintenace 3. 通訊演算法設計開發 4. 數位電路設計及驗證流程

Be in charge of one of below items. 1. Digital IP coding (AMBA, Peripheral, MAC, Modem..) 2. SoC architecture define 3. MAC Layer protocol architecture define 4. Audio codec coding (I2S, SPDIF...) 5. Digital signal processing (Filter.. ) 6. IC design integration (top integration/synthesis/timing closure/DFT) Extra skill is plus. 1. Familiar with Zigbee, Bluetooth or WiFi system is plus. 2. Familiar with audio related processing is plus. 3. Familiar with Perl/Makefile/tcl is plus. 4. The passion to create a wonderful thing.

1. SerDes CTRL IP RTL 開發與維護 (例如LPDDR､UFS､NAND Controller...) 2. 設計驗證 3. FPGA相關設計與實作 以上工作依個人意願酌情分配

【成為円星人】 円星科技由一群專業與充滿熱情的夥伴創立於2011年，為積體電路矽智財設計服務業之新秀，秉持著『成為半導體業最值得信賴之IP公司』的願景，追求永續經營與成長。 誠摯歡迎您成為円星人，加入我們，站上國際舞台！ 一起共同打拚，以精品文化之精神，創造價值，追求卓越！ 【職務簡介】 M31主要業務為向 IC 設計業者和晶圓代工廠授權 IP，此職務為負責高速介面 IP（High Speed Interface IP）開發相關的數位RD職缺。 【將負責的工作內容】 1. RTL design & verification 2. Customer support and debug 3. MIPI,USB, PCIE等高速介面IP開發。 4. 不同製程的IP Porting。 5. PHY Test Chip整合。 【條件與特質】 1. 具備數位設計流程經驗 (Synthesis/LEC/DFT/ATPG/STA) 2. 熟悉完整的Tape out flow 3. 熟悉MIPI,USB,DDR(LPDDR)相關高速混合信號介面(PHY)尤佳 4. 有數位IC設計工程師相關工作經歷3年以上 5. 電機電子/資訊工程碩士畢業 如果您有以上相關經驗且對此職缺有興趣，歡迎投遞您的履歷！

1.IP 產品驗證與分析 2.基礎儀器操作使用(示波器/訊號產生器) 3.量測報告製作與整理 4.Python 程式設計與開發

工作項目： 1. HS design verification. 2. 開發 USB3.2及 PCIe4.0 3. DV協助 HS & RFC. 應徵條件： 1. 碩士以上; 電機工程、電信工程、電控工程、電子工程、資訊工程、自動控制、通訊工程相關科系畢業為主。 2. 具 HS/SERDES/DSP相關電路設計經驗者尤佳。 3. 具 design verification經驗者尤佳。

1. 負責數位IC設計整合: a. 依客戶需求設計整合IC功能、工作頻率、介面規格、消耗功率等基本規格 b. 完成SoC系統架構設計，並依功能單元運作屬性區分區塊規格 c. 使用Verilog/VHDL編程內部功能並撰寫RTL code 2. 負責功能驗證與除錯 a. 制定功能驗證計畫 b. 審核驗證計畫的完整性和正確性 c. 進行基本模擬，確認RTL code的功能 d. RTL code寫入FPGA晶片連接系統測試，驗證RTL code 3. 負責時序分析與功耗管理 a. 產出邏輯閘級電路連線網表(netlist) b. 進行SoC系統的時序分析 c. 進行SoC系統的功耗分析 4. 其它主管交辦事項 【必要條件】 1. 電機、電子、資訊工程或相關科系，碩士以上學歷 2. 三年以上 SoC 設計或整合經驗 3. 熟悉CPU子系統設計整合 a. 熟悉 ARM 架構， b. 對 RISC-V 架構有基本認識 4. 熟悉數位IC前端設計流程，如RTL design、Lint/CDC、Synthesis、STA、LEC、ECO等 5. 具類比IP整合相關經驗，例如PHY、Serdes、PLL等 6. 熟悉IC後段設計流程，如DFT、MBIST、P&R、post-cilicon system level debugging等

[job description] Wolley is seeking candidates for a digital design engineer position. You will join an experienced team designing next-generation memory, storage controllers, and high-speed interface standard. You will also contribute to design concept discussion, architecture definition, as well as design implementation. ‧ Architecture design and RTL implementation ‧ System bus and related peripheral designs ‧ SoC and emulation platform design ‧ SoC system performance analysis [Requirement] 1. Bachelor's or Master's degree in Electrical Engineering or related fields 2. Familiar with RTL design, SystemVerilog, front-end design flow 3. The following working knowledge is desired: * Python programming * TCL scripting * Universal Verification Methodology (UVM) * Low power design and analysis

1. IC產品之研發與應用設計 2. 建立IC產品基礎規格並設計IC電路 3. 降低產品成本，提高IC品質，支援軟/硬體開發 4. 熟數位IC設計及相關工具 Verilog HDL、Cadence IES simulator 、FPGA tools、Synopsys DC

【工作內容】 • Work with team members and apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market • Provide the technical leadership to the DV team for the project • Work independently on various DV tasks and provide technical guidance to the DV team. • Be involved technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup 【職務條件】 • Master’s degree in Electrical Engineering, Computer Science, or related. • Good understanding of ASIC design verification flow. • RTL coding with Verilog/System Verilog and familiar with front-end design flow and C/C++ programming experiences. • Knowledge of Perl, OVL, SVA, SV, UVM, OVM, script programming, etc. 【其他條件】 • MSEE with a minimum of 5 years, or BSEE with a minimum of 8 years of experience in digital ASIC/SOC design verification • MS/BS degree in EE or CS with expertise in digital IP/SOC design verification.

負責數位IP演算法, 與數位工程師共同開發影像處理電路

a. Job Description: We are looking for a highly motivated RTL Designer to join our team in developing high-performance digital IPs. The ideal candidate will have experience in Register Transfer Level (RTL) design and verification, with a strong understanding of digital logic, microarchitecture, and ASIC/FPGA development processes. The role involves designing and verifying custom hardware IPs for cutting-edge applications. b. Verification: Develop and execute test plans to verify functionality, performance, and power requirements. Create testbenches using SystemVerilog/UVM for functional verification. Perform simulation, debugging, and root cause analysis for design issues. Conduct code coverage and functional coverage analysis to ensure comprehensive testing. Collaborate with verification and firmware teams to validate IP functionality. c. Qualifications: Bachelor’s/Master’s degree in Electrical Engineering, Computer Engineering, or a related field. 2+ years of experience in RTL design and verification. Proficiency in Verilog, SystemVerilog Strong understanding of digital design concepts, including pipelining, clock domains, and low-power design techniques. Experience with simulation tools (e.g., ModelSim, VCS, Questa) and formal verification techniques. Familiarity with UVM methodology and testbench development. Knowledge of scripting (Python, TCL, Perl, Shell) for automation. Experience with FPGA or ASIC development flows, including synthesis and timing analysis. Strong debugging and problem-solving skills. Excellent communication and teamwork abilities. - Non smoking

【產品線描述】 1. AMOLED, AR, VR, TDDI等面板驅動IC與觸控IC設計 2. 頂級系統廠ASIC產品合作開發 【工作說明】 1. 高速介面設計 2. 記憶體控制單元設計 3. 面板時序電路設計 4. 面板顯示優化控制單元設計 【必要條件】 1. MS degree in EE fields 2. Good at digital IC front-end design flow such as Verilog RTL design, Synopsys Design compiler, LEC, PrimeTime STA and FPGA 3. Must be a good team player with strong desire to succeed.