「Product Engineer (Innovus)」的相似工作

Position Description Develop PEGASUS/PVS DRC, FILL, LVS, LPE rule decks and RCX flow for worldwide foundries. Manage onsite technical qualification to ensure both PEGASUS/PVS decks and tools are officially qualified by foundries. Collaborate closely with early adoption customers to track and resolve product issues Establish communication channels with R&D to capture customer needs and requirement spec. Work with R&D to enhance and improve PEGASUS/PVS, positioning it as a leading edge Physical Verification tool Position Requirements B.S. in Electrical Engineering (EE), Computer Science (CS), or related area (or equivalent) and 3 - 5 years of experience with Physical Verification tool support/development OR M.S. in EE or CS, or related area (or equivalent) and 1 - 3 years of experience with Physical Verification tool support/development Profound knowledge with Foundry Design Rules and semiconductor fabrication process Ability to develop PEGASUS/PVS rule deck for worldwide foundries, ensuring quality, performance, and compliance with schedules and qualification requirements. Proficiency in TCL and PERL scripting is required Strong English communication skills. Software development experience preferred; familiarity with Cadence SKILL programming is a plus. Experience with IC design and CAD support is advantageous.

1. Deliver the power analysis (IR-drop/EM) methodology and flow 2. Develop or integrate digital design flow/tools with Cadence methodologies and technologies 3. Collaborate with R&D and customers to deliver high quality Cadence Voltus Platform solutions to mutual customers. 4. To support key customer engagements on the business increase. 5. Have real design experience on Power Network analysis 6. To play a leading role among other team members, while receive little instruction on routine and general assignments. 7. Ability to analyze, communicate and lead resolution of complex technical issues for customers and team members. 8. Proactively seeks more information to address issues/problems. Understands how and where to obtain and utilize resources effectively to resolve issues and problems

請務必投遞官網(13021): https://careers.synopsys.com/job/hsinchu/applications-engineering-staff-engineer/44408/87733350400 You Are: You are an innovative and resourceful engineer with a deep curiosity for solving complex technical challenges at the intersection of hardware and software. With a strong foundation in Electronic Engineering, Computer Science, or a related field, you are adept at leveraging your programming expertise—whether in Python, Tcl, Perl, or similar languages—to streamline and enhance engineering workflows. Your experience within UNIX/Linux environments equips you to navigate high-performance computing scenarios with ease. You thrive in collaborative, cross-functional teams and are energized by the opportunity to work closely with top-tier foundry partners and leading fabless companies. Your keen understanding of physical verification flows—such as DRC, LVS, PERC, FILL, and DFM—sets you apart, and you are eager to deepen your expertise in SoC physical design enablement, process effect analysis, and signoff. You are detail-oriented, capable of producing clear technical documentation, and communicate with clarity and empathy across diverse audiences. What You’ll Be Doing: 1.Delivering advanced physical verification solutions (DRC/LVS/PERC/Fill) for top-tier foundries and key fabless customers, ensuring high-quality silicon signoff. 2.Developing and validating process design kits (PDKs) and verification methodologies in collaboration with R&D and customer teams. 3.Partnering with R&D to innovate and improve Synopsys tools and flows, contributing to the evolution of physical verification technologies. 4.Providing hands-on customer support, troubleshooting issues, and delivering timely resolutions that enhance customer satisfaction and product adoption. 5.Coordinating with internal teams, including product managers and end-users, to align on best practices and ensure seamless integration of new technologies. 6.Documenting technical solutions, validation methods, and customer workflows for knowledge sharing and process improvement. 7.Staying up to date on industry trends and applying new insights to continuously optimize verification processes and tools. The Impact You Will Have: Accelerate the adoption and success of Synopsys physical verification products in leading-edge semiconductor manufacturing processes. Drive the development of robust PDKs and methodologies that enable customers to achieve first-time-right silicon. Enhance the quality and reliability of Synopsys verification tools through direct feedback and collaborative innovation with R&D teams. Strengthen Synopsys’ reputation as a trusted partner to top-tier foundries and fabless customers worldwide. Facilitate faster product cycles and reduced time-to-market for customers by delivering efficient and effective signoff solutions. What You’ll Need: BS or MS degree in Electronic Engineering, Computer Science, or a related field. Proficiency in at least one programming language, such as Python, Tcl, or Perl. Hands-on experience with UNIX/Linux environments and command-line tools. Familiarity with physical verification flows (DRC, LVS, PERC, FILL, DFM) and understanding of complex layout/electrical design rules. Strong investigative, analytical, and problem-solving abilities, with a passion for learning new technologies. Ability to produce clear, concise technical documentation and validation reports. Prior knowledge of tool/runset development/support and experience with SoC physical design is a plus.

若有興趣者，請務必上傳英文履歷至官網,否則不予受理(職缺代碼12936): https://careers.synopsys.com/job/hsinchu/r-and-d-engineering-staff-engineer-zebu-12936/44408/87200702592 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: A highly skilled engineer with a deep understanding of simulation, emulation, and compiler technologies. You bring extensive experience with HDL languages like Verilog and have previously worked with VCS and ZeBu platforms. Your proficiency in programming languages such as C/C++ is complemented by a strong grasp of data structures and algorithms, including graph theory. You excel in designing modular, scalable software architectures and optimizing software performance through multi-threading and operating system concepts. Your familiarity with version control systems like Perforce and Git enables you to manage code efficiently and collaborate seamlessly with other teams. You are an effective communicator, able to convey complex technical concepts clearly and work collaboratively in a dynamic environment. Your passion for technology drives you to stay updated with industry trends, and you actively mentor and guide junior engineers, fostering a culture of continuous learning and innovation. What You’ll Be Doing: 1.Designing and developing high-performance software for Synopsys' simulation and emulation platforms, including VCS and ZeBu. 2.Collaborating with cross-functional teams to enhance product capabilities and performance. 3.Conducting comprehensive research and analysis to address complex engineering challenges. 4.Leading project initiatives, ensuring timely and high-quality deliverables. Mentoring junior engineers and fostering a culture of continuous learning and innovation. 5.Integrating new technologies and staying abreast of industry trends to drive continuous improvement. The Impact You Will Have: 1.Enhancing the performance and reliability of emulation platforms used for cutting-edge silicon chips. 2.Driving the development of next-generation simulation and emulation tools. 3.Improving the usability and adoption of Synopsys products across various industries. 4.Contributing to a collaborative and innovative engineering culture within the team. 5.Advancing the future of technology and connectivity through continuous innovation. 6.Delivering high-quality, performance-optimized software solutions that elevate Synopsys' success. What You’ll Need: *CS or EE master's degree or above at least five of relevant experience. *Proficiency in programming languages: C/C++. *Strong understanding of data structures and algorithms, including graph theory. *Experience with hardware description languages like Verilog and scripting languages like TCL. *Prior experience with HDL simulation and emulation platforms, including VCS and ZeBu. *Familiarity with version control systems like Perforce and Git. *Ability to design and implement modular, scalable software architecture. *Proficiency in multi-threading and operating system concepts for software *performance optimization. Who You Are: A proactive and innovative thinker with a passion for technology. A collaborative team player who thrives in a dynamic environment. An effective communicator with strong interpersonal skills. A mentor and leader who inspires and guides junior engineers. A continuous learner who stays updated with industry trends and advancements.

1.製造流程建立與SOP撰寫、維護 2.產品導入及問題處置追蹤 3.良率提升及製程優化 4.客訴、不良分析與處置 5.工程變更導入及追蹤. 6.設備治工具開發驗證及維護管理與異常檢修 7.工廠與產品開發人員之間的溝通協調 8.其他主管交辦事項

Job Description: At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Virtuoso Custom Layout Interactive and Assisted Route team is looking for exceptional individuals skilled in C++ development, IC layout techniques and custom circuit design. You'll focus on Virtuoso interactive and assisted route software development. You're also responsible for implementing, verifying and maintaining physical design software modules for custom integrated circuits in the Advance Node areas of Virtuoso Layout Suite. Requirements: 1) MS/PhD in EE/ECE/CS graduate or BS with at least 2 years software development experience. 2) Strong C++ development and object oriented design skills. 3) Software development experience in EDA is preferred. 4) Experience with UNIX and/or LINUX software development platforms. 5) Good English communication skill. 6) Familiarity with Cadence's Virtuoso layout framework, SKILL language programming or OpenAccess database will be a plus We're doing work that matters. Help us solve what others can't.

1.新產品試作及量產導入 2.試產報告、技轉、產品導入 3.生產異常排除相關數據問題收集分析 4.優化SOP.標準工時、製程改善 5.生產製程治具製作 6.自動化設備維護

1. 專案開發前期: 協同SA訂定規格/設計環境建構/競品特性分析/協同PM訂定開發時程表 2. 專案開發期間: 支援電路設計及整合/定期招開設計檢查會議/定期追蹤開發進度/確保專案各站點完成時程/準備各站點檢查資料及文件/測試相關資料的準備 3. 專案開發後期: 分析CP驗證數據/確保良率達標/協同SA,RD,TE進行除錯分析/確保達送樣標準

1.新評估項目導入，稽核及品質相關會議安排與執行，有品質管理經驗佳。 2.具有客戶服務意識和了解客戶需求能力，能夠主動回應客戶並提供有效的解決方案。 3.廠商客戶品質問題的處理與回覆、後續的分析追蹤與執行。 4.撰寫與審核8D Report，具備英文撰寫能力及良好跨部門溝通能力，針對品質問題進行追蹤處理。 5.協同維護氣體鋼瓶及化學品更換，氣體及化學產品出貨與倉儲管理。 6.異常排除，緊急應變處理，需多元性發展以協助其他專案報告及設備相關維護活動。 7.主管交辦事務執行。

• Co-work with package design team to complete a substrate layout that will meet the design objectives for performance, cost and quality. • Co-work with SOC team to complete Bump floorplan and RDL routing. • Power mesh/power density flow development and related flow development and enhancement. • Provide power plan result for PR team. • Chip IR signoff : provide the result and solution to APR & package team • Chip level PEM/SEM simulation and fixing plan providing. • SIR/DIR/PEM/SEM result data review and verification. • Familiar with Voltus / Redhawk experience is required.

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. Job Overview: Work with the manager to deliver integrated and effective marketing programs and achieve corporate marketing objectives. Execute media relations and social media management. Collaborate with corporate marketing, sales, product teams, and external partners to ensure consistent messaging. Job Responsibilities: Events Management: Assist the manager in planning, organizing, and executing marketing activities that drive brand awareness and demand generation at all kinds of events, including large-scale conferences, seminars, workshops, and product campaigns. Work with the manager to execute the event strategy, event theme, logistics, vendor management, on-site operations, and post-event reporting. Media Relations, Social Media Management and Public Communications: Execute the media outreach strategies to increase overall brand awareness and thought leadership. Execute localized social media strategies to promote brand visibility, product launch, and event campaigns. Assist the manager to build and maintain relationships with key media, government stakeholders and industry alliances. Assist the manager on CSR/ESG branding management and activities to support Corp and local ESG branding visibility. Cross team collaboration and reporting: Work closely with field sales, regional business and engineering leaders, and corporate teams to align marketing plans, activities, and marketing assets support. Support logistics and purchasing processes for marketing campaigns if needed. Job Qualifications: Bachelor’s degree in Marketing, Communications, Business or related field. 3-6 years’ experience in the field of marketing, events management, or media relations, preferably in the technology and semiconductor industry. Able to work independently and hands-on logistics support on campaigns and promotions.

※ Job Contents: 1. Perform Netlist-to-GDS design flow, including floorplanning, placement, timing optimization, clock tree synthesis and routing. 2. Support STA timing analysis and fixing 3. Perform physical verification, including DRC, LVS, IR drop and DFM analysis. ※ Requirements: 1. Familiar with Cadence Innovus or Synopsys ICC2/Fusion Compiler. 2. TOEIC 730~855 is preferred. 3. Have experiences in 16/12/7/5nm IC design experiences will be plus.

【工作內容】 • Work with team members and apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market • Provide the technical leadership to the DV team for the project • Work independently on various DV tasks and provide technical guidance to the DV team. • Be involved technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup 【職務條件】 • Master’s degree in Electrical Engineering, Computer Science, or related. • Good understanding of ASIC design verification flow. • RTL coding with Verilog/System Verilog and familiar with front-end design flow and C/C++ programming experiences. • Knowledge of Perl, OVL, SVA, SV, UVM, OVM, script programming, etc. 【其他條件】 • MSEE with a minimum of 5 years, or BSEE with a minimum of 8 years of experience in digital ASIC/SOC design verification • MS/BS degree in EE or CS with expertise in digital IP/SOC design verification.

1. Knowledge and experience of circuit design guideline, latch up, EM and ESD checking rule. 2. Calibre DRC/LVS/PERC Command File maintain and writing. 3. Physical Verification flow enhancement and deployment. 4. CAD Utility development. 5. Soft skill ability like TCL, Perl, shell script

At cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. You’ll develop state-of-the-art library characterization tools for our worldwide customers in an exciting and innovative environment. Position Responsibilities:  Full time in industry leading software development  Involvement in local customer engagements in cooperation with global teams  Develop new product features, including invention, design and implementation new algorithms to build industry leading products Desired Qualifications:  Experiences in EDA/IC industry  Experiences in library characterization, spice simulation, or transistor level timing  Effective communication skills, passion to drive a project and to win customers Additional Job Description  Experience in developing library characterization or circuit simulation software  High level understanding of SPICE simulation transistor models  Experience with distributed programming, database design, and cloud APIs for distributed computing  Proficiency designing data structures, algorithms, and software engineering principles  Experience in developing Machine Learning technology and deploy it at customers

1. 分析製程流程與產品規格，協助新產品導入，確保產品符合高品質標準。 2. 運用 DOE（實驗設計）、FMEA、SPC 等品質管理工具，提升製程穩定性與產品良率。 3. 進行生產異常分析，提出改善方案並推動製程優化。 4. 能閱讀與理解機械圖與電路圖，協助跨部門問題解決。 5. 積極參與專案推動，確保計畫順利落地。

1. 參與公司數位後段設計 之產品開發 2. 熟悉與維護 並參與 新流程之開發

Responsibility: 1. Power User of Andes CPU and SoC Platform IP Products  Test and feedback on RTL simulation, synthesis and FPGA prototype flows in the product packages  Proofread product documents  Create application notes and technical white papers 2. Solution Provider of Andes CPU and SoC Platform IP Products  Assist Service team to provide consultations to customers  Assist Service team to resolve customers' issues during their product developments  Collect and forward customers' feedback and requirements to product development teams Qualification: 1. Experience in 32/64-bit CPU based SoC developments 2. Experience in RTL simulation, synthesis, PPA analysis and FPGA validation 3. Familiar with computer architecture 4. Familiar with at least one generic programming language

1.客戶新規模具裝機與模壓測試、並製作測試結果報告回覆日本原廠。 2.客戶模壓品質問題處理與對應、製作報告並與日本原廠商討對策解決問題。 3.新規與追加工模具零件量測與品質檢查。 4.支援日本原廠工程師新模具開發與試模。

1. 數位設計電路開發與維護。 2. SoC系統設計電路開發與維護。 3. 數位設計與晶片系統設計技術諮詢。 4. 其它主管交辦事項。