「Physical Verification Engineer」的相似工作

(1)Must have BS in CS/EE of relevant experience in IC design field. (2)Familiar with IC design flow, placement and route (P&R), and layout. (3)Circuit knowledge and logic design relevant experience would be a plus.

Responsibilities: • Develop integrated verification environment. • Verify designs with system verilog and system verilog assertion. • Build, maintain and upgrade testbenches and their components using UVM-based methods. • Check functional coverage and code coverage • Create controlled random testcases. Pre-debug and provide debug reports. • Scripting experience using scripting languages like Perl and Python.

【工作內容】 • 我們正在尋找具備先進製程經驗的 IC Layout 工程師，加入團隊後可以參與高階SoC /Analog IP 的實體實現，並負責以下工作： -Mixed-Mode FinFET Layout 設計與繪製，確保電路佈局在效能、面積與可靠性之間取得最佳平衡。 -進行 FinFET 製程相關的 DRC / LVS / ERC 驗證，確保設計符合法規與 Foundry 要求。 -熟悉 XRC & EM/IR 分析流程，進行可靠性評估，並針對潛在問題提出改善方案。 【職務條件】 • 必備條件：具備 FinFET 製程經驗，能獨立進行版圖設計與驗證。 -具備類比電路佈局經驗，了解電路特性與佈局考量，能與設計工程師密切合作。 -具備良好的溝通能力與團隊合作精神，能在專案時程內交付高品質成果。

1. Design verification with SystemVerilog/UVM, C/C++ 2. Integration test environment with VIP 3. Develop checker and scoreboard. 4. Verify design with SystemVerilog assertion. 5. Test plan for a verification task. [Requirement] 1. Familiar with SystemVerilog HDL, OOP, Python, TCL, and shell programming. 2. Better to have SoC design and bus concept.

1. 參與公司數位後段設計 之產品開發 2. 熟悉與維護 並參與 新流程之開發

【工作內容】 • Work with team members and apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market • Provide the technical leadership to the DV team for the project • Work independently on various DV tasks and provide technical guidance to the DV team. • Be involved technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup 【職務條件】 • Master’s degree in Electrical Engineering, Computer Science, or related. • Good understanding of ASIC design verification flow. • RTL coding with Verilog/System Verilog and familiar with front-end design flow and C/C++ programming experiences. • Knowledge of Perl, OVL, SVA, SV, UVM, OVM, script programming, etc. 【其他條件】 • MSEE with a minimum of 5 years, or BSEE with a minimum of 8 years of experience in digital ASIC/SOC design verification • MS/BS degree in EE or CS with expertise in digital IP/SOC design verification.

We are seeking a highly motivated Design Verification Engineer to join our dynamic team. You will be responsible for ensuring the functional correctness of complex digital designs using industry-leading verification methodologies such as UVM, Formal Verification, and Coverage-Driven Verification. 【Key Responsibilities】 · Develop detailed verification plans based on design specifications and architectural documents. · Build and maintain System Verilog UVM-based testbenches for SoC/Subsystem/IP-level verification. · Write constrained-random and directed test cases to validate functionality, performance, and corner-case scenarios. · Perform coverage analysis (functional coverage, code coverage, assertions coverage) and drive towards coverage closure. · Apply Formal Verification techniques (e.g., property checking, connectivity checking) where applicable. · Support simulation regression runs and maintain automation scripts (Perl/Python/TCL/Makefile). · Participate in design and verification reviews, providing valuable feedback to improve quality.

制定全面的 x86 CPU 驗證計劃，確保驗證流程嚴謹且高效。 規劃並建立 UVM、 Constraint Random、Formal 驗證環境架構，提升驗證效率。 指導與培訓 Junior DV 團隊成員，確保驗證目標的順利達成。

1. Knowledgeable in power analysis and IR/EM methodologies, with hands-on experience using Ptpx, Redhawk, or Voltus for power and IREM evaluation. 2. Familiar with the integrated circuit (IC) design flow, capable of performing design, optimization, and verification using tools such as ICC2 or INNOVUS. 3. Experience in developing automation scripts using Python, Perl, TCL, or Shell is a strong plus. 4. Experienced in IO/IP planning, including bump/PAD placement and RDL routing is a plus. 5. Experienced in fundamental circuit structures (e.g., standard cells, IO), with the ability to simulate basic circuits using Hspice or Spectre is a plus.

1. 具備 Layout 工作經驗，想挑戰SOC晶片(Mix mode / HV / SRAM / Power / ESD..)並有志往Physical design 發展者 2. 需懂ESD / 製程觀念 / 電路原理 3. 具Tapeout 量產經驗，獨立處理 Whole chip 能力尤佳 4. 熟以下流程尤佳：Laker L3+ HSIM simulation + IREM分析 5. 強烈要求穩定性高，積極度高，做事態度需具備高度 Commitment 決心與毅力，具備高度 EQ/AQ，擁有團隊合作的精神 6. 工作地點：此職缺在【台南(樹谷園區)、新竹】皆設有相關單位。

【主要工作內容】 1.Netlist to GDS, including floorplan/powerplan/physical synthesis/clock tree synthesis & routing 2.Chip level physical verification, including DRC/LVS/DFM & tapeout 3.IR-Drop analysis 【需求條件】 1.有使用過ICC/ICC2/laker, 曾做過fully layout & chip level PV 2.工作態度積極認真, 有獨自解決問題能力

1. 需具備類比IC Layout、BCD Prcoess整合經驗。 2. 需負責全晶片整合佈局和驗證 3. 熟悉Virtuoso, Laker, Calibre使用 4. 此職務上班地點在新竹辦公室

擴大規模，大量徵才 1.專業Full Custom IC layout 2.對IC Layout 有興趣者, 須具有清晰之 邏輯觀念

類比/馬達/電源管理 IC Layout

1. 數位設計電路開發與維護。 2. SoC系統設計電路開發與維護。 3. 數位設計與晶片系統設計技術諮詢。 4. 其它主管交辦事項。

※ Job Contents: 1. Perform Netlist-to-GDS design flow, including floorplanning, placement, timing optimization, clock tree synthesis and routing. 2. Support STA timing analysis and fixing 3. Perform physical verification, including DRC, LVS, IR drop and DFM analysis. ※ Requirements: 1. Familiar with Cadence Innovus or Synopsys ICC2/Fusion Compiler. 2. TOEIC 730~855 is preferred. 3. Have experiences in 16/12/7/5nm IC design experiences will be plus.

【成為円星人】 円星科技由一群專業與充滿熱情的夥伴創立於2011年，為積體電路矽智財設計服務業之新秀，秉持著『成為半導體業最值得信賴之IP公司』的願景，追求永續經營與成長。 誠摯歡迎您成為円星人，加入我們，站上國際舞台！ 一起共同打拚，以精品文化之精神，創造價值，追求卓越！ 【職務簡介】 M31主要業務為向 IC 設計業者和晶圓代工廠授權 IP，此職務為負責IO電路設計相關之職缺。 【將負責的工作內容】 1. ESD/Latch-up防護設計與驗證 2. I/O電路設計 (Fail safe, Tolerant, Cascade) 3. 高速IO 電路設計 (DDR, ONFI, SDIO) 4. LDO/POR/VDT 電路設計 5. XTAL oscillator 電路設計 6. Analog circuit, IO, PISI, ESD Basic/Advanced Knowledge 【條件與特質】 1. Analog circuit, IO circuit design and simulation 2. 擅長工具-SPICE, Virtuoso 3. 有IO 相關工作經歷3年以上, Analog/IO Basic/Advanced Knowledge 如果您有以上相關經驗且對此職缺有興趣，歡迎投遞您的履歷！

1.負責部分全定製版圖的設計和驗證。 2.確保IC佈局符合Circuit Designer設計需求及產品、製程、電氣的規範。

1) FPGA synthesis, verification, and env. maintain一年以上FPGA使用經驗 2) CP/PT pattern creation and chip validation 3) 熟CMOS原理&CCM設計 4) 懂基礎C/C++,基礎Linux. 5) 編寫技術文件 ,電路設計,IC 訊號測試&功能量測

1. FrontEnd flow development. 2. Project support and consultant. 3. Develop CAD utility, design automation 4. Work with different process nodes, develop the design flow and methodology