「PLL設計工程師」的相似工作

Job description Join our innovative team specializing in cutting-edge embedded memory solutions. We are seeking Analog Circuit Engineers to play a key role in the design and development of high-performance embedded DRAM and associated peripheral circuits. In this position, you will be responsible for the complete cycle of DRAM circuit design and simulation verification. Your tasks will involve developing novel circuit topologies, transistor-level design, optimizing performance metrics, and ensuring robust functionality through extensive simulations using industry-standard EDA tools. Required qualifications include a strong technical background in Electrical Engineering, Electronics Engineering, Computer Engineering, Physics, or a closely related field. Candidates must possess demonstrated, significant experience in DRAM circuit design and comprehensive simulation verification methodologies. Ideally, candidates will have proven design experience in specific DRAM-related circuit blocks, including but not limited to: Row and Column Decoder circuits Control path logic DC-DC converters, Charge Pumps, and Bandgap References Delay Locked Loops (DLLs) and Phase Locked Loops (PLLs) Negative voltage generators (NVG) and other critical peripheral circuits This is an excellent opportunity to contribute to state-of-the-art embedded memory designs in a dynamic, collaborative environment. If you are a skilled analog designer passionate about solving complex challenges in DRAM circuitry, we encourage you to apply and help shape the future of embedded memory technology.

1. SAR ADC / Current steering DAC/ SDM ADC/ DAC related 2. Analog Baseband related 3. 據有類比整合相關經驗佳

【工作職責 (Responsibilities)】： ★ Build & innovate on high-speed analog/mixed-signal circuits such as PCIe/DDR/HDMI... transmitter and receiver in deep sub-micron CMOS technology for integration in SoC products. ★ Work with digital team on specification definition ★ Create behavior model for analog/digital evaluation ★ Compliance test for SerDes IP 【符合條件 (Qualifications)】： ★ Familiar with high speed SerDes specification ★ Familiar with IC/SoC design flow ★ Familiar with analog simulation flow ★ Experience SerDes analog blocks design ★ Must be good team player 【必須條件 (Minimum Qualifications)】： ★ Familiar with Audio analog IP design, such as Preamp/DAC/ADC (including SAR and DSM) 【優秀條件 (Preferred Qualifications)】： ★ Familiar with controller integration ★ Familiar with other baseband analog IP design, such as BGAP/LDO/XTAL/PLL, etc. ★ Familiar with ESD, Latch up, I/O ★ Familiar with layout flow

1.設計高速 SERDES 電路及相關Analop IP (TX,RX,PLL,I/O....) 2.熟悉以下電路尤佳 OSC, TX, DDR, Equalizer, PLL, DLL, CDR, Memory, Buck .

1. Main responsibility is to design analog IPs in MCU such as adc/dac, pll, osc, por, ldo 2. 具備DC-DC Converter, Buck相關電路設計 2. Responsible for analog IP design, verification plan, test plan, document 3. Communicate with system, layout and digital engineer to ensure high quality --------------------------------------------------------------------------------------- 雅特力科技創立於2016年，為智原科技子公司。 【Artery雅特力】即將在台上市的IC設計公司，主要產品為32bit ARM core base MCU 公司網址：https://www.arterychip.com 關於雅特力：https://www.104.com.tw/company/1a2x6blojm

*大學月薪33800元 / 碩士月薪38600元 1.申請與執行研究計畫。 2.負責報帳、經費申請、物品建檔等行政工作。 3.操作並維護計劃或實驗相關的設備與儀器。 4.協助資料收集和資料分析。 5.編輯、撰寫計畫報告書。

1. PLL design 2. High speed receiver design (1.5Gbps/4Gbps/5.4Gbps/8.1Gbps/12Gbps) 3. High speed transmitter design (1.5Gbps/4Gbps/5.4Gbps/8.1Gbps/12Gbps) 4. eDP receiver 5. V-by-One receiver 6. MIPI D-PHY 7. HDMI Receiver 8. HDMI Transmitter 9. LCD P2P interface Transmitter 10. LDO and DCDC design 工作地點:新竹/台南

1. Memory circuit design and verification. 2. Gate-level verilog simulation against to the datasheet. 3. Failure mode analysis.

【成為円星人】 円星科技由一群專業與充滿熱情的夥伴創立於2011年，為積體電路矽智財設計服務業之新秀，秉持著『成為半導體業最值得信賴之IP公司』的願景，追求永續經營與成長。 誠摯歡迎您成為円星人，加入我們，站上國際舞台！ 一起共同打拚，以精品文化之精神，創造價值，追求卓越！ 【職務簡介】 M31主要業務為向 IC 設計業者和晶圓代工廠授權 IP，此職務為負責高速介面 IP（High Speed Interface IP）, 包含USB. PCIE, MIPI MPHY, CPHY, DPHY等SERDES IP和類比 IP（Analog IP）, 包含ADC, DAC, PLL, PVT sensor的類比IC設計工程師職缺。 【將負責的工作內容】 1. Mixed-Signal & Analog Circuits Design (LDO, OPA, Bandgap, ADC/DAC, etc) 2. High Speed Interface Analog Design (TX, RX, etc) 3. Clocking related：PLL/CDR 【條件與特質】 1. 有類比IC設計工程師相關工作經歷3年以上 2. 電機電子/資訊工程碩士畢業 如果您有以上相關經驗且對此職缺有興趣，歡迎投遞您的履歷！

Digital IC design engineer - Familiar with Verilog RTL coding - Familiar with digital design flow (pre-layout simulation, timing constraint, synthesis, post-layout simulation) - Will be working on high speed Serdes IPs - Experience or interest in all-digital PLLs or clock-data recovery circuits is a big plus

We are seeking a skilled Analog IC Design Engineer with expertise in MIPI TX/ PLL design and sensor readout circuits. The ideal candidate will possess a strong foundation in analog design and a passion for developing cutting-edge solutions in a collaborative environment. 1.Design and implement MIPI TX and PLL circuits for high-speed data transmission. 2.Develop charge pump and LDO (Low Dropout Regulator) circuits to ensure efficient power management. 3.Design and optimize oscillator (OSC) circuits for precise timing applications. 4.Create sensor readout circuits, including CDS (Correlated Double Sampling), TDC (Time-to-Digital Converter), ramp circuits, DAC (Digital-to-Analog Converter), and comparators. 5.Collaborate with system engineers to define specifications and ensure alignment with overall project requirements. 6.Perform circuit simulations and analyses using tools such as Cadence, Spectre, or HSPICE. 7.Conduct design verification and validation through prototyping and testing. 8.Optimize designs for performance, power efficiency, and reliability. 9.Participate in design reviews and contribute to project documentation. 10.Provide support during the layout and fabrication process. Preferred Qualifications: 1.Familiarity with IP design principles. 2.Experience with mixed-signal circuits. 3.Knowledge of low-noise and high-speed design techniques.

We are looking for a senior engineer to be part of the mixed-signal design team building next generation NVLINK. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. You will be responsible for the development and implementation of high speed interfaces, including TX/RX/Clocking/PLL. You will have hands on experience taking innovative integrated circuit designs at data rates of 50Gbps and higher from concept through silicon characterization. What you will be dong: - Define circuit requirements and complete design from schematic, layout, and verification to characterization. - Conduct schematic design of deep-submicron CMOS technologies using Spectre, Hspice or like. - Take responsibility for the architecture, transistor design and verification using industry standard EDA tools such as Cadence virtuoso. - Optimize circuit to meet the specifications for system performance. - Work with layout engineers by providing detailed floorplan and guidance for matching and high-speed routings. - Provide support for post-silicon bring-up and debugging. What we need to see: - Master of Science or foreign equivalent degree in Electrical Engineering, Computer Engineering or related field with strong analog design background. - Minimum 2 years analog design experience in industry - CMOS Analog / Mixed Signal Circuit Design Experience in deep sub-micron process (especially in FINFET) - Experience with design and verification tools (Cadence's IC design environment, analog circuit simulation tools like Spectre, HSpice, Finesim, XA) - Experience in crafting test bench environments for component and top level circuit verification - Behavioral modeling of analog and digital circuits - Strong debugging and analytical skills - Analog simulation for noise analysis, loop stability analysis, ac/dc/tran analysis, monte-carlo, etc. - Strong communication skills and ability & desire to work as a great teammate are huge plus. - All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, citizenship, disability or protected veteran status.

1. 高速介面 (SerDes) 類比電路設計 2. Circuit design of CTLE/CDR/DFE/PLL/HDMI2.1 TX /USB3.2 RX /USB3.2 TX 

Job desicription: Our Design Team specializes in the challenging field of Non-Volatile Memory (NVM) IC circuit design. We are actively seeking an experienced Analog Circuit Design Engineer to contribute to our cutting-edge developments in embedded NVM solutions and surrounding circuitry. As a key member of our team, you will be responsible for the design, verification, and debugging of essential analog building blocks like Bandgap references, LDOs, and Charge Pumps. A significant part of your role will involve designing critical memory peripheral circuits for NVM IP and test chips, including Array interfaces, Decoding logic, and Sense Amplifiers. Your responsibilities will span the design lifecycle, from contributing to IP specifications and core circuit design to ensuring performance through layout optimization and comprehensive corner simulations of NVM IPs. We are looking for candidates with proven expertise in analog circuit design, ideally with prior experience in embedded memory or NVM technologies. If you are an experienced analog designer eager to tackle complex challenges in non-volatile memory, we encourage you to apply and help shape the future of memory technology.

1. NVM電路開發設計。 2. NVM週邊類比電路開發設計與佈局優化。 3. NVM電路整合開發設計。 4. 協助NVM測試晶片偵錯、驗證。 5. 協助客戶嵌入使用以及導入量產NVM IP產品。 研究所以上電子/電機相關系所畢，專長於類比電路設計、固態電子或功率半導體元件設計，有下線經驗者優先考慮。

專長為RF/類比IC電路(LDO, OP, charge Pump, DC/DC converter,PA/LNA bias design)設計及測試，具有量產經驗為佳。

1. 觸控IC、TDDI或指紋辨識 IC 開發經驗 2. ADC或sensor IP 開發經驗 3. TFT-LCD或OLED Display driver IC 開發經驗 4. Charge pump、LDO、Source driver、Gate driver、High speed interface、OSC、BGR 相關開發經驗 5. 工作地點：【台南、新竹、台北】 以上其中任何一項相關者佳。

• Circuit design of One-Time Programmable (OTP) IPs in state of art process technologies for commercial, automotive and industrial applications • Leading & working within design team with full IP and technology ownership and responsibilities, from bit cell development to IP design and release • Supervision of layout activities in all blocks, optimization of circuit performance, area and power. • Collaborating with test engineers and product engineers to expedite silicon evaluation process • Working closely with Sales & CE (Customer Engineer) in promotion of company’s OTP IPs, and in fulfilling the need of (existing and prospective) customers 1. NVM (Non-Volatile Memory) 電路開發設計 2. NVM週邊類比電路開發設計與佈局優化 3. NVM電路整合開發設計 4. 協助NVM測試晶片驗證、偵錯 5. OTP IP 之專案負責人，偕同公司之銷售代表及客戶工程師，協助客戶嵌入使用以及導入量產NVM IP產品

Job Description: As a team member of analog product business group, this role will support Analog IC circuit design of mixed-signal ICs, such as sensors, motor drivers, data converters. Key Responsibilities: 1. Co-work with talented design teams to develop high performance sensor related integrated circuits and products, such as Hall effect sensor, temperature sensor. 2. Contribute to chip architecture and circuit design decisions 3. Collaborate with validation, product engineering and test engineering teams to enable successful transfer to production 4. Also, will be responsible for circuit requirements definition, design, simulation and analysis, layout/test support, documentation and customer support for sensor applications. Qualifications: 1. Demonstrate strong analytical and problem-solving skills 2. Strong time management skills that enable on-time project delivery 3. In depth working experience with Cadence composer and Virtuoso, Spectre, HSpice and mixed-signal design flow. 4. Experience in lab measurement and equipment. 5. Self-starter. Passionate about creative work. Good communication skills and team player. Able to take the initiative and drive for results.

The successful candidate shall possess the capability to design and analyze high speed, high performance analog / mixed signal circuits, including data converters, PLLs, and SERDES, in advanced CMOS FinFET technologies. She or he shall bring the design all the way to production. Imagine being part of a team that is fundamentally changing the way people communicate, the way they collaborate, the way they watch TV and explore the universe through the internet. Utilizing our uniquely differentiated technology, we have created an Intelligent Transport Network with more speed, capacity and scalability than ever before. Imagine a world with unlimited bandwidth. The network of tomorrow will allow for content and creativity limited only by the imaginations of its users. If this is something that interests you, that excites you, come take a look at a team not bound by large company obstacles and bureaucracy, where an idea today can be set in motion tomorrow. Come take a look at Infinera! Engaging in the high-speed analog circuit design, you have the chance to create the technical differentiation for Infinera to hold the market leadership. We together will revolutionize the era of efficient high speed transmission by building the cutting-edge circuitry. Your Key Responsibilities Would Include: Design, implement, and simulate the functionality and performance of various high-speed analog circuits, including the ADCs and DACs; Create the layout floor plans to optimize the overall performance; Supervise the layout activities and give concise guidelines to layout engineers, need to be hands on in drawing layout if necessary; Exploring the trade-offs of the different topologies and propose the best solution to achieve or exceed the requirements in terms of power/area/linearity/bandwidth, etc. Develop the analog testing plans and work with the PE/TE teams to characterize the functionality and performance of the products to ensure the quality; Need to support and comply with the team’s design methodologies and release flows. Mandatory Knowledge/Skills/Abilities: Must be extremely familiar with essential CAD tools, such as Cadence Virtuoso, Spectre, Incisive, Calibre, EMX, and Totem EM/IR, etc. Must have a proven tracking record of designing complex analog / mixed signal IPs or chips in deep submicron CMOS technologies. Must have experiences in bringing high performance analog IPs including but not limited to high-speed ADC, high-speed DAC, and high-frequency low-jitter PLL to production. Must have a decent understanding in CMOS analog / mixed signal design methodologies and circuit analysis; Must have a good understanding of device physics and the impacts of layout effects; Able to perform the behavioral modeling the blocks and circuits with Verilog-A or Verilog-AMS; Collaborative with other local or remote team members in a fast-paced professional environment. Preferred Knowledge/Skill/Abilities: Fluent in verbal and written communications; Independently resolves issues and conquer design challenges; Self-motivated and detail-oriented; Has the knowledge of (optical) communication theories and Matlab coding. Education and Experience Requirements: Minimum Requirement for Principal Design Engineer: M.S. in E.E. with 12+ years’ experience, or Ph.D. in E.E. with 8+ years’ experience