「Senior Analog Design Engineer (High Speed/SerDes) [Taipei]」的相似工作

1. 有USB3.1 TX/RX PHY, CDR, PLL, CTLE, DFE, FFE 的經驗 2. MIPI PHY IP 設計經驗 3. Tapeout experience on 28nm or below 4. 技術指導及專案管理 *第1、2項經驗擇一即可

The successful candidate shall possess the capability to design and analyze high speed, high performance analog / mixed signal circuits, including data converters, PLLs, and SERDES, in advanced CMOS FinFET technologies. She or he shall bring the design all the way to production. Imagine being part of a team that is fundamentally changing the way people communicate, the way they collaborate, the way they watch TV and explore the universe through the internet. Utilizing our uniquely differentiated technology, we have created an Intelligent Transport Network with more speed, capacity and scalability than ever before. Imagine a world with unlimited bandwidth. The network of tomorrow will allow for content and creativity limited only by the imaginations of its users. If this is something that interests you, that excites you, come take a look at a team not bound by large company obstacles and bureaucracy, where an idea today can be set in motion tomorrow. Come take a look at Infinera! Engaging in the high-speed analog circuit design, you have the chance to create the technical differentiation for Infinera to hold the market leadership. We together will revolutionize the era of efficient high speed transmission by building the cutting-edge circuitry. Your Key Responsibilities Would Include: Design, implement, and simulate the functionality and performance of various high-speed analog circuits, including the ADCs and DACs; Create the layout floor plans to optimize the overall performance; Supervise the layout activities and give concise guidelines to layout engineers, need to be hands on in drawing layout if necessary; Exploring the trade-offs of the different topologies and propose the best solution to achieve or exceed the requirements in terms of power/area/linearity/bandwidth, etc. Develop the analog testing plans and work with the PE/TE teams to characterize the functionality and performance of the products to ensure the quality; Need to support and comply with the team’s design methodologies and release flows. Mandatory Knowledge/Skills/Abilities: Must be extremely familiar with essential CAD tools, such as Cadence Virtuoso, Spectre, Incisive, Calibre, EMX, and Totem EM/IR, etc. Must have a proven tracking record of designing complex analog / mixed signal IPs or chips in deep submicron CMOS technologies. Must have experiences in bringing high performance analog IPs including but not limited to high-speed ADC, high-speed DAC, and high-frequency low-jitter PLL to production. Must have a decent understanding in CMOS analog / mixed signal design methodologies and circuit analysis; Must have a good understanding of device physics and the impacts of layout effects; Able to perform the behavioral modeling the blocks and circuits with Verilog-A or Verilog-AMS; Collaborative with other local or remote team members in a fast-paced professional environment. Preferred Knowledge/Skill/Abilities: Fluent in verbal and written communications; Independently resolves issues and conquer design challenges; Self-motivated and detail-oriented; Has the knowledge of (optical) communication theories and Matlab coding. Education and Experience Requirements: Minimum Requirement for Principal Design Engineer: M.S. in E.E. with 12+ years’ experience, or Ph.D. in E.E. with 8+ years’ experience

1.設計高速 SERDES 電路及相關Analop IP (TX,RX,PLL,I/O....) 2.熟悉以下電路尤佳 OSC, TX, DDR, Equalizer, PLL, DLL, CDR, Memory, Buck .

1. NVM電路開發設計。 2. NVM週邊類比電路開發設計與佈局優化。 3. NVM電路整合開發設計。 4. 協助NVM測試晶片偵錯、驗證。 5. 協助客戶嵌入使用以及導入量產NVM IP產品。 研究所以上電子/電機相關系所畢，專長於類比電路設計、固態電子或功率半導體元件設計，有下線經驗者優先考慮。

1. Main responsibility is to design analog IPs in MCU such as adc/dac, pll, osc, por, ldo 2. 具備DC-DC Converter, Buck相關電路設計 2. Responsible for analog IP design, verification plan, test plan, document 3. Communicate with system, layout and digital engineer to ensure high quality --------------------------------------------------------------------------------------- 雅特力科技創立於2016年，為智原科技子公司。 【Artery雅特力】即將在台上市的IC設計公司，主要產品為32bit ARM core base MCU 公司網址：https://www.arterychip.com 關於雅特力：https://www.104.com.tw/company/1a2x6blojm

1. 具 0~2年數位晶片設計，或有 0~5年類比晶片設計工作經驗。 2. 具備基本數位和類比電路知識，熟習標準晶片設計流程。 3. 熟習業界常用EDA tools, 或Matlab/ Simulink。 4. 研習過CMOS or BiCMOS 類比設計電路課程，對放大器有基礎認識。 5. Experience in these areas is preferred： * BiCMOS or CMOS high-speed (>20Gb/s) circuit, Linear electrical amplifier & equalizer, High-speed (>25G) CDR/PLL/SerDes. * Linear optical laser driver & receiver (TIA + linear amplifier) 本職位負責類比IC電路的設計、驗證和除錯。這是一個高度技術性的職位，對公司的產品開發至關重要。我們正在尋找一位熱愛類比IC設計並具有相關經驗的人才，以推動公司的技術創新和發展。 如果您對這個職位感興趣，請投遞您的履歷表，我們立即與您聯繫。

[General Summary] As a forward-thinking technology company, Augentix advances the limits of innovation in "Industrial and Embedded IoT" to deliver next-generation experiences and accelerate digital transformation toward a smarter, more seamlessly connected world. As a Low Power Architect at Augentix, you will define and drive power-efficient solutions for next-generation embedded vision and AI products. You will work across software and hardware domains, including SoC architecture, firmware, operating systems, and board-level design, to ensure our always-on, battery-powered devices deliver optimal performance under strict energy constraints. Your work will directly impact real-world deployments such as smart cameras, doorbells, and IoT edge nodes. [Responsibilities] ★ Define low power architecture across SoC, firmware, operating system power management, and board level power delivery, with a focus on battery-powered and always-on vision applications. ★ Translate system use cases like video streaming, AI inference, and connectivity into quantitative power budgets and resume-latency targets, for example, achieving sub-20mW standby for a 4G solar camera or a sub-150ms wake-up time for a doorbell-to-preview scenario. ★ Specify power domain partitioning, voltage scaling strategies, and clock and power gating policies for CPU, Bus, memory, ISP, NPU, and other key IPs. ★ Collaborate with SoC and firmware teams to implement DVFS, retention, and deep sleep flows. ★ Guide power modeling, workload analysis, and efficiency validation across software and hardware. ★ Review schematic, layout, and power delivery design to support optimal leakage and efficiency. ★ Validate low power operation across suspend, idle, and runtime use cases on embedded Linux or RTOS. ★ Lead power issue root cause analysis across silicon, firmware, and board. ★ Monitor technology trends and drive roadmap planning for future low power features. ★ Support cross functional alignment on power budgeting, testing, and optimization throughout development. ★ Occasional business travel across APAC and other regions may be required. [Minimum Qualifications] ★ Master's degree in Electrical Engineering, Computer Science, Physics, or a closely related field with 6+ years of relevant experience, or a PhD in a related field with 3+ years of relevant experience. ★ Strong knowledge of SoC power architecture including power islands, retention, DVFS, and gating techniques. ★ Familiarity with embedded power management frameworks and firmware based control. ★ Experience with power estimation tools and correlation against silicon measurements. ★ Understanding of board level power design and integration with PMICs. ★ Ability to debug and optimize power behavior across hardware and software layers. ★ Experience documenting and reviewing architecture level specifications. [Preferred Qualifications] ★ Proven experience in optimizing power for camera, video processing, or AI/ML accelerator workloads. ★ Background in power constrained products such as wearables, sensors, or portable AI devices. ★ Knowledge of multi rail sequencing, leakage control, and thermal aware power management. ★ Experience with Linux power subsystems including cpufreq, suspend, idle, and thermal frameworks. ★ Involvement in platform level power benchmarking and profiling. ★ Strong communication and collaboration skills across engineering disciplines. ★ Comfortable working in a globally distributed, cross-disciplinary engineering team.

Job description Join our innovative team specializing in cutting-edge embedded memory solutions. We are seeking Analog Circuit Engineers to play a key role in the design and development of high-performance embedded DRAM and associated peripheral circuits. In this position, you will be responsible for the complete cycle of DRAM circuit design and simulation verification. Your tasks will involve developing novel circuit topologies, transistor-level design, optimizing performance metrics, and ensuring robust functionality through extensive simulations using industry-standard EDA tools. Required qualifications include a strong technical background in Electrical Engineering, Electronics Engineering, Computer Engineering, Physics, or a closely related field. Candidates must possess demonstrated, significant experience in DRAM circuit design and comprehensive simulation verification methodologies. Ideally, candidates will have proven design experience in specific DRAM-related circuit blocks, including but not limited to: Row and Column Decoder circuits Control path logic DC-DC converters, Charge Pumps, and Bandgap References Delay Locked Loops (DLLs) and Phase Locked Loops (PLLs) Negative voltage generators (NVG) and other critical peripheral circuits This is an excellent opportunity to contribute to state-of-the-art embedded memory designs in a dynamic, collaborative environment. If you are a skilled analog designer passionate about solving complex challenges in DRAM circuitry, we encourage you to apply and help shape the future of embedded memory technology.

analog circuit design and verification

1. 類比電路設計開發 2. 感測器元件開發與整合 3. 具CIS影像感測器相關類比IC電路設計驗驗者佳

1. 高速介面 (SerDes) 類比電路設計 2. Circuit design of CTLE/CDR/DFE/PLL/HDMI2.1 TX /USB3.2 RX /USB3.2 TX 

Job Description: As a team member of analog product business group, this role will support Analog IC circuit design of mixed-signal ICs, such as sensors, motor drivers, data converters. Key Responsibilities: 1. Co-work with talented design teams to develop high performance sensor related integrated circuits and products, such as Hall effect sensor, temperature sensor. 2. Contribute to chip architecture and circuit design decisions 3. Collaborate with validation, product engineering and test engineering teams to enable successful transfer to production 4. Also, will be responsible for circuit requirements definition, design, simulation and analysis, layout/test support, documentation and customer support for sensor applications. Qualifications: 1. Demonstrate strong analytical and problem-solving skills 2. Strong time management skills that enable on-time project delivery 3. In depth working experience with Cadence composer and Virtuoso, Spectre, HSpice and mixed-signal design flow. 4. Experience in lab measurement and equipment. 5. Self-starter. Passionate about creative work. Good communication skills and team player. Able to take the initiative and drive for results.

• Circuit design of One-Time Programmable (OTP) IPs in state of art process technologies for commercial, automotive and industrial applications • Leading & working within design team with full IP and technology ownership and responsibilities, from bit cell development to IP design and release • Supervision of layout activities in all blocks, optimization of circuit performance, area and power. • Collaborating with test engineers and product engineers to expedite silicon evaluation process • Working closely with Sales & CE (Customer Engineer) in promotion of company’s OTP IPs, and in fulfilling the need of (existing and prospective) customers 1. NVM (Non-Volatile Memory) 電路開發設計 2. NVM週邊類比電路開發設計與佈局優化 3. NVM電路整合開發設計 4. 協助NVM測試晶片驗證、偵錯 5. OTP IP 之專案負責人，偕同公司之銷售代表及客戶工程師，協助客戶嵌入使用以及導入量產NVM IP產品

1. 類比電路設計, 如Bias、Bandgap 、OPAmp、LDO 、ADC/DAC 2. Hspice模擬 3. 類比IC設計整合及設計流程 4. 類比IP的規劃與維護 5. Whole Chip Layout Floor Plan設計

1. CMOS影像感測器之Pixel, ADC, DAC, PLL等類比電路設計開發 2. 混合式訊號嵌入式設計, 低電壓、省電、低雜訊之類比IC設計者尤佳

【成為円星人】 円星科技由一群專業與充滿熱情的夥伴創立於2011年，為積體電路矽智財設計服務業之新秀，秉持著『成為半導體業最值得信賴之IP公司』的願景，追求永續經營與成長。 誠摯歡迎您成為円星人，加入我們，站上國際舞台！ 一起共同打拚，以精品文化之精神，創造價值，追求卓越！ 【職務簡介】 M31主要業務為向 IC 設計業者和晶圓代工廠授權 IP，此職務為負責高速介面 IP（High Speed Interface IP）, 包含USB. PCIE, MIPI MPHY, CPHY, DPHY等SERDES IP和類比 IP（Analog IP）, 包含ADC, DAC, PLL, PVT sensor的類比IC設計工程師職缺。 【將負責的工作內容】 1. Mixed-Signal & Analog Circuits Design (LDO, OPA, Bandgap, ADC/DAC, etc) 2. High Speed Interface Analog Design (TX, RX, etc) 3. Clocking related：PLL/CDR 【條件與特質】 1. 有類比IC設計工程師相關工作經歷3年以上 2. 電機電子/資訊工程碩士畢業 如果您有以上相關經驗且對此職缺有興趣，歡迎投遞您的履歷！

[General Summary] As a forward-thinking technology company, Augentix advances the limits of innovation in "Industrial and Embedded IoT" to deliver next-generation experiences and accelerate digital transformation toward a smarter, more seamlessly connected world. As a software engineer at Augentix, you will contribute to the design, development, and validation of embedded device drivers across Linux and RTOS platforms. Your work will enable high-performance imaging pipelines and sensor interfaces for camera-centric products in industrial and edge environments. Senior engineers will play a key role in architecture design, bring-up, system integration, and mentoring junior developers. [Responsibilities] ★ Design, develop, and maintain audio device driver firmware for embedded camera and IoT systems. ★ Implement and optimize real-time audio processing algorithms (e.g., voice enhancement, noise suppression). ★ Analyze and resolve system-level audio quality and performance issues. ★ Maintain and enhance existing DSP frameworks and audio processing chains. ★ Conduct system performance profiling and apply targeted optimizations. ★ Collaborate with cross-functional teams (hardware, systems, driver, and test) to deliver production-ready solutions. ★ Occasional business travel across APAC and other regions may be required. [Minimum Qualifications] ★ Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related field with 3+ years of relevant experience. ★ Experience in embedded software or DSP firmware development. ★ Proficiency in C programming for embedded systems. ★ Solid understanding of digital signal processing fundamentals with a focus on audio. ★ Experience debugging and optimizing audio pipelines in resource-constrained environments. [Preferred Qualifications] ★ Experience with Linux kernel audio subsystems, particularly ALSA. ★ Knowledge of embedded processor architecture and writing low-latency, real-time code. ★ Hands-on experience with FPGA-based system validation. ★ Familiarity with system-level profiling tools and audio performance tuning. ★ Comfortable working in a globally distributed, cross-disciplinary engineering team.

1. SAR ADC / Current steering DAC/ SDM ADC/ DAC related 2. Analog Baseband related 3. 據有類比整合相關經驗佳

1.Work with team members and apply design techniques to work on different phases of complex logic design for ASIC/SOC project. 2. Working on the following tasks from time to time: HDL coding, documentation, RTL quality check, cooperate with back-end engineer etc.

*大學月薪33800元 / 碩士月薪38600元 1.申請與執行研究計畫。 2.負責報帳、經費申請、物品建檔等行政工作。 3.操作並維護計劃或實驗相關的設備與儀器。 4.協助資料收集和資料分析。 5.編輯、撰寫計畫報告書。