「Senior Analog Design Engineer (High Speed/SerDes) [Taipei]」的相似工作

※實際任用職稱依個人相關經歷敘薪。 1. 熟悉Display Driver IC 原理. 2. 可獨立完成Charge Pump design. 3. 可獨立完成Band Gap, Regulators , LDO circuit design. 4. 熟悉類比電子電路專業知識如OP-AMP的設計 5 .個性主動積極、熱誠 、樂觀 . 6. 8~10年經驗 7. mipi. lvds frontend 設計與 debug 經驗尤佳

【職位描述】 設計RVI公司新創的光通訊引擎(Optical Engine)類比電路設計工程師，負責設計、開發、測試、優化和調試類比電路及系統，產品矽中介層、玻璃中介層與高階基板。負責從概念到生產的電路設計，確保光引擎達到品質和性能標準。 【主要職責】 1.設計和開發創新的類比電路和系統，應用於光引擎和相關技術領域。 2.測試、優化和調試類比電路，確保其性能符合設計規範和功能需求。 3.與跨部門團隊合作，包括系統工程師、軟體工程師、光學工程師及其他專業人員，共同實現產品開發目標。 4.與客戶密切合作，理解其需求並提供技術支持和解決方案。 5.制定和執行測試計畫，分析測試數據，並提出改進建議。 6.保持對最新技術趨勢的了解，並將其應用於產品設計中以提升競爭力。 Position Description: As an Analog Circuit Design Engineer at RVI, you will be a key contributor to the development of our next-generation Optical Engine. You will be responsible for designing, developing, testing, optimizing, and debugging analog circuits and systems used in advanced optical communication modules, including silicon interposers, glass interposers, and high-end substrates. This role spans from initial concept to mass production, ensuring the performance and quality of the optical engine meet industry standards. Key Responsibilities: 1.Design and develop innovative analog circuits and systems for optical engines and related applications. 2.Test, optimize, and debug analog circuits to ensure performance meets design specifications and functional requirements. 3.Collaborate with cross-functional teams, including system engineers, software engineers, and optical engineers, to achieve product development goals. 4.Work closely with customers to understand their requirements and provide technical support and tailored solutions. 5.Develop and execute test plans, analyze test data, and propose design improvements. 6.Stay updated on emerging technologies and incorporate relevant advancements into circuit design to enhance product competitiveness.

Responsible for developing custom IP for SoC design from specification definition, circuit design to testing, and familiar with component and process characteristics.

The successful candidate shall possess the capability to design and analyze high speed, high performance analog / mixed signal circuits, including data converters, PLLs, and SERDES, in advanced CMOS FinFET technologies. She or he shall bring the design all the way to production. Imagine being part of a team that is fundamentally changing the way people communicate, the way they collaborate, the way they watch TV and explore the universe through the internet. Utilizing our uniquely differentiated technology, we have created an Intelligent Transport Network with more speed, capacity and scalability than ever before. Imagine a world with unlimited bandwidth. The network of tomorrow will allow for content and creativity limited only by the imaginations of its users. If this is something that interests you, that excites you, come take a look at a team not bound by large company obstacles and bureaucracy, where an idea today can be set in motion tomorrow. Come take a look at Infinera! Engaging in the high-speed analog circuit design, you have the chance to create the technical differentiation for Infinera to hold the market leadership. We together will revolutionize the era of efficient high speed transmission by building the cutting-edge circuitry. Your Key Responsibilities Would Include: Design, implement, and simulate the functionality and performance of various high-speed analog circuits, including the ADCs and DACs; Create the layout floor plans to optimize the overall performance; Supervise the layout activities and give concise guidelines to layout engineers, need to be hands on in drawing layout if necessary; Exploring the trade-offs of the different topologies and propose the best solution to achieve or exceed the requirements in terms of power/area/linearity/bandwidth, etc. Develop the analog testing plans and work with the PE/TE teams to characterize the functionality and performance of the products to ensure the quality; Need to support and comply with the team’s design methodologies and release flows. Mandatory Knowledge/Skills/Abilities: Must be extremely familiar with essential CAD tools, such as Cadence Virtuoso, Spectre, Incisive, Calibre, EMX, and Totem EM/IR, etc. Must have a proven tracking record of designing complex analog / mixed signal IPs or chips in deep submicron CMOS technologies. Must have experiences in bringing high performance analog IPs including but not limited to high-speed ADC, high-speed DAC, and high-frequency low-jitter PLL to production. Must have a decent understanding in CMOS analog / mixed signal design methodologies and circuit analysis; Must have a good understanding of device physics and the impacts of layout effects; Able to perform the behavioral modeling the blocks and circuits with Verilog-A or Verilog-AMS; Collaborative with other local or remote team members in a fast-paced professional environment. Preferred Knowledge/Skill/Abilities: Fluent in verbal and written communications; Independently resolves issues and conquer design challenges; Self-motivated and detail-oriented; Has the knowledge of (optical) communication theories and Matlab coding. Education and Experience Requirements: Minimum Requirement for Principal Design Engineer: M.S. in E.E. with 12+ years’ experience, or Ph.D. in E.E. with 8+ years’ experience

Digital IC design engineer - Familiar with Verilog RTL coding - Familiar with digital design flow (pre-layout simulation, timing constraint, synthesis, post-layout simulation) - Will be working on high speed Serdes IPs - Experience or interest in all-digital PLLs or clock-data recovery circuits is a big plus

我們專注於能源晶片與深度演算法的融合創新，誠徵類比IC演算法工程師，將傳統的手工類比設計流程轉化為自動化的智慧演算法，讓電路設計更高效、更穩定，推動類比設計的未來。 你將負責： 開發電路拓撲分析演算法 設計 sizing 最佳化演算法（基於 gm/Id methodology 等） 將手工設計流程轉化為程式化流程 協助建立類比IC設計自動化工具 與軟體團隊合作進行演算法驗證與優化 熟練使用 Vibe Coding 工具（Cursor、Github Copilot、Claude… 等）更佳 我們期待你具備： 類比IC設計實務經驗 熟悉運算放大器、ADC/DAC、電源管理電路等拓撲設計 精通 SPICE 模擬與電路參數萃取 深度理解 sizing methodology（如 gm/Id 設計法） 能清楚闡述設計 trade-off 與電路原理 加分條件： 具備 Python 程式能力 有將手工設計方法轉換為程式實現的經驗 具備統計分析能力（Monte Carlo / corner analysis） 有 EDA 工具 API 開發經驗 熟悉圖論演算法與資料結構 如果你熱愛把設計方法變成程式，並用演算法重新定義類比IC設計的可能性，歡迎加入我們！

1.熟悉類比混合訊號IP開發, 例如PLL，LDO，USB PHY，MIPI PHY 2.對類比電路設計充滿熱忱者

[General Summary] As a forward-thinking technology company, Augentix advances the limits of innovation in "Industrial and Embedded IoT" to deliver next-generation experiences and accelerate digital transformation toward a smarter, more seamlessly connected world. We are seeking a PCB Design Engineer with strong theoretical foundation and simulation driven design methodology to lead high speed board level development. You will be responsible for defining and verifying board level electrical design, ensuring optimal signal integrity across multiple high speed interfaces. You will be supported by experienced layout engineers capable of implementing your design guidance and constraints, allowing you to focus on PCB circuit design and system validation. This position offers the opportunity to build structured PCB design practices, improve team capability, and drive electrical excellence through direct ownership of simulation and cross team collaboration. [Responsibilities] ★ Lead system level PCB electrical design for interfaces such as LPDDR4/5, USB 3.x, SDIO 3.x, MIPI and Ethernet. ★ Define PCB stack up and routing strategy to meet signal integrity objectives. ★ Perform circuit level simulations using tools such as PSpice. ★ Own schematic level electrical planning and define layout constraints for critical signal groups. ★ Provide guidance to supporting layout engineers to ensure adherence to electrical rules and best practices. ★ Correlate simulation results with lab measurements and assist in electrical issue root cause analysis. ★ Document simulation methodology constraint guidelines and validation reports. ★ Occasional business travel across APAC and other regions may be required. [Minimum Qualifications] ★ Familiarity with differential and single ended routing across LPDDR4/5, USB 3.x, SDIO 3.x, MIPI and Ethernet. ★ Proficiency with layout tools such as Allegro. ★ Exposure to EMI mitigation techniques and hands on experience in EMI pre compliance testing. ★ Demonstrated ability to lead layout teams or mentor junior engineers in constraint based PCB design. ★ Ability to create structured documentation and design guidelines to scale internal processes. ★ Strong debugging and problem solving skills with working knowledge of firmware and software to support system level root cause analysis. ★ Comfortable working in a globally distributed, cross-disciplinary engineering team.

We are seeking a skilled Analog IC Design Engineer with expertise in MIPI TX/ PLL design and sensor readout circuits. The ideal candidate will possess a strong foundation in analog design and a passion for developing cutting-edge solutions in a collaborative environment. 1.Design and implement MIPI TX and PLL circuits for high-speed data transmission. 2.Develop charge pump and LDO (Low Dropout Regulator) circuits to ensure efficient power management. 3.Design and optimize oscillator (OSC) circuits for precise timing applications. 4.Create sensor readout circuits, including CDS (Correlated Double Sampling), TDC (Time-to-Digital Converter), ramp circuits, DAC (Digital-to-Analog Converter), and comparators. 5.Collaborate with system engineers to define specifications and ensure alignment with overall project requirements. 6.Perform circuit simulations and analyses using tools such as Cadence, Spectre, or HSPICE. 7.Conduct design verification and validation through prototyping and testing. 8.Optimize designs for performance, power efficiency, and reliability. 9.Participate in design reviews and contribute to project documentation. 10.Provide support during the layout and fabrication process. Preferred Qualifications: 1.Familiarity with IP design principles. 2.Experience with mixed-signal circuits. 3.Knowledge of low-noise and high-speed design techniques.

1. SAR ADC / Current steering DAC/ SDM ADC/ DAC related 2. Analog Baseband related 3. 據有類比整合相關經驗佳

[General Summary] As a forward-thinking technology company, Augentix advances the limits of innovation in "Industrial and Embedded IoT" to deliver next-generation experiences and accelerate digital transformation toward a smarter, more seamlessly connected world. As a DRAM System Engineer at Augentix, you will be responsible for bringing up and validating DRAM subsystems across our embedded platforms. You will work at the intersection of hardware and low-level software to ensure memory stability, performance, and power efficiency under demanding workloads. This role offers the opportunity to lead system-level debugging, performance tuning, and test automation for DDR3/LPDDR3/DDR4/LPDDR4 memory interfaces, while collaborating closely with hardware, SoC, and kernel teams across the product development lifecycle. [Responsibilities] ★ Lead DRAM bring-up and validation for DDR3/LPDDR3/DDR4/LPDDR4 on new hardware platforms. ★ Configure memory controller and PHY registers to meet JEDEC specs and system performance requirements. ★ Perform signal integrity validation and work with hardware team on layout constraints and SI/PI tuning. ★ Conduct stress tests and margin sweeps (e.g., memory hammer test, data retention, read/write window tuning). ★ Analyze system-level memory stability and performance under boot-up, suspend/resume, and runtime workloads. ★ Collaborate with SoC, PCB, firmware, and kernel teams to debug memory-related issues. ★ Develop and maintain automated test flows and diagnostics for DRAM reliability and performance. ★ Occasional business travel across APAC and other regions may be required. [Minimum Qualifications] ★ Master's degree in Electrical Engineering or a related field with 3+ years of relevant experience, or a PhD in a related field. ★ Strong understanding of DDR3/LPDDR3/DDR4/LPDDR4 specifications, timing parameters, and calibration schemes. ★ Experience in configuring DRAM registers and bring-up on embedded platforms. ★ Familiar with memory controller architecture and PHY interface tuning. ★ Skilled in using logic analyzers, oscilloscopes, and memory test equipment. ★ Comfortable with Linux-based embedded systems and debugging low-level software interactions with DRAM. [Preferred Qualifications] ★ Experience debugging kernel panics or stability issues caused by DRAM misconfiguration. ★ Familiarity with memory low-power states, self-refresh, and power-saving strategies. ★ Knowledge of post-silicon validation, including test pattern development and validation coverage planning. ★ Worked with DRAM vendors to understand datasheets, tuning recommendations, and errata. Comfortable working in a globally distributed, cross-disciplinary engineering team.

記憶體power system 設計 『具工作經驗者，薪資另議』

Job description Join our innovative team specializing in cutting-edge embedded memory solutions. We are seeking Analog Circuit Engineers to play a key role in the design and development of high-performance embedded DRAM and associated peripheral circuits. In this position, you will be responsible for the complete cycle of DRAM circuit design and simulation verification. Your tasks will involve developing novel circuit topologies, transistor-level design, optimizing performance metrics, and ensuring robust functionality through extensive simulations using industry-standard EDA tools. Required qualifications include a strong technical background in Electrical Engineering, Electronics Engineering, Computer Engineering, Physics, or a closely related field. Candidates must possess demonstrated, significant experience in DRAM circuit design and comprehensive simulation verification methodologies. Ideally, candidates will have proven design experience in specific DRAM-related circuit blocks, including but not limited to: Row and Column Decoder circuits Control path logic DC-DC converters, Charge Pumps, and Bandgap References Delay Locked Loops (DLLs) and Phase Locked Loops (PLLs) Negative voltage generators (NVG) and other critical peripheral circuits This is an excellent opportunity to contribute to state-of-the-art embedded memory designs in a dynamic, collaborative environment. If you are a skilled analog designer passionate about solving complex challenges in DRAM circuitry, we encourage you to apply and help shape the future of embedded memory technology.

【產品線描述】 TV & Video Solution: 1. LCD TV Controller 2. Frame Rate Converter (FRC) / MEMC 3. TCON 4. LCD Monitor Controller 5. Large Format Display Controller Imaging Solution: 1. Car DVR 2. Consumer & Professional Surveillance Camera 3. Sport DV 4. Drone SoC 【職務說明】 Confirm circuit/system specification and achieve design from schematic, layout, and silicon characterization. - Mixed-signal design of deep-submicron CMOS technologies using EDA like Spectre, Hspice . - Optimize circuit to meet the specifications / power consumption for system performance. - Co-work with layout engineers for IP physical layout and PostSim / IR analysis / EM analysis - Silicon debugging / Mass-production supprt You will be responsible for the design and physical implementation of SERDES building blocks, for example: Analog front end, CTLE, DFE, PLL, DLL, LCVCO, CDR, Data-Dmux, Data-Serialization, Wire-Line Transmitter, FFE, Bandgap, POR, LDO, GPIO, 5V Tolerance IO, XTAL, real time clock(RTC), etc… Candidate will be participating in mixed mode circuit design. Experience in the following design is preferred. LVDS, HDMI, DisplayPort, VByOne, USB, MIPI C/D PHY receiver design. HDMI/V-By-One(VBO)/DisplayPort/Panel P2P Interfaces (USIT/iSP/BOE/EPI/LVDS) High-speed Transmitter design. DDR4/DDR3/DDR2/LPDDR4(X)/LPDDR3 PHY or I/O circuit design. And other High speed SERDES IP. 【必要條件】 - Master of Science / Above degree in Electrical Engineering, strong mixed-signal design concept. - Mixed Signal Circuit Design Experience in deep sub-micron process (22nm / FINFET). - Familiar with design and simulation tools (Cadence's design environment, Circuit simulation : Spectre, HSpice, Finesim, ADiT) - Verilog-A and MATLAB behavioral modeling of analog and digital circuits. - Strong debugging and analytical skills. - Clear communication skills and team work ability are necessary.

1. 類比電路設計開發 2. 感測器元件開發與整合 3. 具CIS影像感測器相關類比IC電路設計經驗者佳

1. CMOS影像感測器之Pixel, ADC, DAC, PLL等類比電路設計開發 2. 混合式訊號嵌入式設計, 低電壓、省電、低雜訊之類比IC設計者尤佳

[General Summary] As a forward-thinking technology company, Augentix advances the limits of innovation in "Industrial and Embedded IoT" to deliver next-generation experiences and accelerate digital transformation toward a smarter, more seamlessly connected world. As a software engineer at Augentix, you will contribute to the design, development, and validation of device drivers enabling hardware-accelerated video encoding across Linux and RTOS platforms. You will work on low-level bring-up and system integration of codecs such as H.264, H.265, and JPEG, collaborating with hardware, multimedia, and system teams to deliver high-performance, low-latency solutions for camera and vision platforms. Senior engineers are expected to take architectural ownership and mentor junior contributors. [Responsibilities] ★ Design and implement device drivers for encoder-related subsystems (H.264, H.265, JPEG) on Linux and RTOS environments. ★ Port and adapt drivers to run across diverse operating systems and platforms. ★ Perform low-level debugging and hardware-software integration on pre-silicon (FPGA) and production silicon. ★ Conduct system-level performance profiling, debugging, and power/memory optimizations. ★ Work closely with hardware, system, and test teams to ensure robust and production-ready camera enablement. ★ Support secure boot, fast boot, and always-on-video (AOV) scenarios. ★ Collaborate with cross-functional teams to support platform bring-up, tuning, and field issue resolution. ★ Occasional business travel across APAC and other regions may be required. [Minimum Qualifications] ★ Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related field. ★ Proficiency in C programming and embedded software development. ★ Experience with Linux kernel and/or RTOS (FreeRTOS, Zephyr) driver development. ★ Familiarity with device driver architecture, memory-mapped I/O, interrupts, and synchronization. ★ Ability to work across user space and kernel space boundaries. [Preferred Qualifications] ★ Experience with ISP and video encoder pipelines. ★ Understanding of SoC-level architecture including ARM, MMU/IOMMU/SMMU. ★ Experience with FPGA bring-up or hardware emulation platforms. ★ Exposure to real-time constraints and low-latency driver design. ★ Familiarity with encoder standards for H.264, H.265, and JPEG. ★ Familiarity with OSD on video encoders is a plus. ★ Knowledge of secure boot, fast boot and always-on-video (AOV) is a plus. ★ Comfortable working in a globally distributed, cross-disciplinary engineering team.

1. 具 0~2年數位晶片設計，或有 0~5年類比晶片設計工作經驗。 2. 具備基本數位和類比電路知識，熟習標準晶片設計流程。 3. 熟習業界常用EDA tools, 或Matlab/ Simulink。 4. 研習過CMOS or BiCMOS 類比設計電路課程，對放大器有基礎認識。 5. Experience in these areas is preferred： * BiCMOS or CMOS high-speed (>20Gb/s) circuit, Linear electrical amplifier & equalizer, High-speed (>25G) CDR/PLL/SerDes. * Linear optical laser driver & receiver (TIA + linear amplifier) 本職位負責類比IC電路的設計、驗證和除錯。這是一個高度技術性的職位，對公司的產品開發至關重要。我們正在尋找一位熱愛類比IC設計並具有相關經驗的人才，以推動公司的技術創新和發展。 如果您對這個職位感興趣，請投遞您的履歷表，我們立即與您聯繫。

1. 類比電路設計, 如Bias、Bandgap 、OPAmp、LDO 、ADC/DAC 2. Hspice模擬 3. 類比IC設計整合及設計流程 4. 類比IP的規劃與維護 5. Whole Chip Layout Floor Plan設計

[General Summary] As a forward-thinking technology company, Augentix advances the limits of innovation in "Industrial and Embedded IoT" to deliver next-generation experiences and accelerate digital transformation toward a smarter, more seamlessly connected world. As a Low Power Architect at Augentix, you will define and drive power-efficient solutions for next-generation embedded vision and AI products. You will work across software and hardware domains, including SoC architecture, firmware, operating systems, and board-level design, to ensure our always-on, battery-powered devices deliver optimal performance under strict energy constraints. Your work will directly impact real-world deployments such as smart cameras, doorbells, and IoT edge nodes. [Responsibilities] ★ Define low power architecture across SoC, firmware, operating system power management, and board level power delivery, with a focus on battery-powered and always-on vision applications. ★ Translate system use cases like video streaming, AI inference, and connectivity into quantitative power budgets and resume-latency targets, for example, achieving sub-20mW standby for a 4G solar camera or a sub-150ms wake-up time for a doorbell-to-preview scenario. ★ Specify power domain partitioning, voltage scaling strategies, and clock and power gating policies for CPU, Bus, memory, ISP, NPU, and other key IPs. ★ Collaborate with SoC and firmware teams to implement DVFS, retention, and deep sleep flows. ★ Guide power modeling, workload analysis, and efficiency validation across software and hardware. ★ Review schematic, layout, and power delivery design to support optimal leakage and efficiency. ★ Validate low power operation across suspend, idle, and runtime use cases on embedded Linux or RTOS. ★ Lead power issue root cause analysis across silicon, firmware, and board. ★ Monitor technology trends and drive roadmap planning for future low power features. ★ Support cross functional alignment on power budgeting, testing, and optimization throughout development. ★ Occasional business travel across APAC and other regions may be required. [Minimum Qualifications] ★ Master's degree in Electrical Engineering, Computer Science, Physics, or a closely related field with 6+ years of relevant experience, or a PhD in a related field with 3+ years of relevant experience. ★ Strong knowledge of SoC power architecture including power islands, retention, DVFS, and gating techniques. ★ Familiarity with embedded power management frameworks and firmware based control. ★ Experience with power estimation tools and correlation against silicon measurements. ★ Understanding of board level power design and integration with PMICs. ★ Ability to debug and optimize power behavior across hardware and software layers. ★ Experience documenting and reviewing architecture level specifications. [Preferred Qualifications] ★ Proven experience in optimizing power for camera, video processing, or AI/ML accelerator workloads. ★ Background in power constrained products such as wearables, sensors, or portable AI devices. ★ Knowledge of multi rail sequencing, leakage control, and thermal aware power management. ★ Experience with Linux power subsystems including cpufreq, suspend, idle, and thermal frameworks. ★ Involvement in platform level power benchmarking and profiling. ★ Strong communication and collaboration skills across engineering disciplines. ★ Comfortable working in a globally distributed, cross-disciplinary engineering team.