「APR Technical Project Leader (Design Service)」的相似工作

DESCRIPTION: 1. Responsible for the physical design process of chip numbers from netlist to GDSII 2. Responsible for interaction with the front-end design team to realize the design convergence and optimization of the front and back ends; Comprehensive, static timing analysis 3. Floor planning, power planning and signoff, place and route, timing closure, chip static timing analysis and physical verification 4. IP integration, synthesis, verification and correction 5. Other Assigned Tasks delivered by the Line Manager QUALIFICATIONS: 1. MS degree in EE or related. 2. Familiar with physical design flow, including hierarchical design and low power design is a plus 3. Familiar with EDA tools, such as SoC Encounter/INNOVUS/ICC/ICC2 is a plus 4. Familiar with computer languages such as Perl/TCL/C-shell 5. Self-motivated with good communication skills and team spirit 6. Ability to understand and articulate technical issues. 7. Fluent English is a plus. 8. Experience in 12/5nm design is a plus.

【主要工作內容】 1.Netlist to GDS, including floorplan/powerplan/physical synthesis/clock tree synthesis & routing 2.Chip level physical verification, including DRC/LVS/DFM & tapeout 3.IR-Drop analysis 【需求條件】 1.有使用過ICC/ICC2/laker, 曾做過fully layout & chip level PV 2.工作態度積極認真, 有獨自解決問題能力

ASIC design engineer responsible for post-RTL design flow. He/She will be responsible for block and /or chip level synthesis, timing closure, DFT generation, and ECOs. The responsibilities include but are not limited to. •    Improve the design methodology and flow. •    Synthesis, timing closure, and DFT support for various types of SerDes IPs ranging from 10Gbps to 224Gbps data rates for different applications. •    Collaborate with Analog/Digital design teams to deliver competitive SerDes IP solutions for all the Marvell product lines. •    Provide support to the product teams, for both pre and post-silicon

(1)Must have BS in CS/EE of relevant experience in IC design field. (2)Familiar with IC design flow, placement and route (P&R), and layout. (3)Circuit knowledge and logic design relevant experience would be a plus.

1. 執行應收帳款、合併報表編製之總帳會計作業。 2. 負責管理報表編製、分析與預算編列。 3. 財報、稅報編製，並協助會計師查帳作業。 4. 年度會計專案業務執行與推動。 5. 主管交辦事項。

【職務內容】 ˙需具備HV經驗 Level Shifter（含 HV Device）、Charge Pump、Source Driver、OpAmp / DAC、TCON（含 Digital Layout + Clock Tree） ˙需具備3-5年Driver相關經驗 ˙需熟悉繞線（Routing） ˙Block-Level設計經驗可 ˙能讀懂 Calibre DRC command file 語法佳 ˙具備28/22nm HV製程經驗佳 ˙無需英文能力，全台灣團隊

【工作內容】 • 我們正在尋找具備先進製程經驗的 IC Layout 工程師，加入團隊後可以參與高階SoC /Analog IP 的實體實現，並負責以下工作： -Mixed-Mode FinFET Layout 設計與繪製，確保電路佈局在效能、面積與可靠性之間取得最佳平衡。 -進行 FinFET 製程相關的 DRC / LVS / ERC 驗證，確保設計符合法規與 Foundry 要求。 -熟悉 XRC & EM/IR 分析流程，進行可靠性評估，並針對潛在問題提出改善方案。 【職務條件】 • 必備條件：具備 FinFET 製程經驗，能獨立進行版圖設計與驗證。 -具備類比電路佈局經驗，了解電路特性與佈局考量，能與設計工程師密切合作。 -具備良好的溝通能力與團隊合作精神，能在專案時程內交付高品質成果。

1. Work on 3~7nm design implementation, methodology, and sign-off 2. Perform synthesis, DFT, floorplan, clock planning, place and route, timing closure, ECO, IR signoff, and physical verification 3. Manage schedule, resolve design and flow issues, drive methodologies and execution

1.Support and maintain EDA tools and flows used in the digital IC implementation. 2.Design and develop methodologies, automation scripts, and design flow. 3.Manage version control system (Git/SVN), issue tracking system, and CI/CD flow. [Requirement] 1.Python/Perl/TCL/Shell programming skills. 2.Familiar with EDA tools for IC design flow. 3.Basic knowledge of Verilog or SystemVerilog HDL.

Job Summary: Layout Engineer will work directly and indirectly with Design / CAD / Layout Manager in development of Mixed-Signal and Analog Integrated Circuits. Individual perform job professionally and independently. The following are the requirements for this job function. Essential Functions: • Chip Planning • Project Schedule / Layout Schedule Estimation • Device Placement on block level according to matching requirements • Block implementations on Top Level • Top Level connections • Signal matching / sensitive nets shielding technique • Chip power / ground planning • Integration of Analog top with Auto-Placement-Routing • Pad / ESD rule and routing / connection • Database DRC & LVS verifications on either DIVA or Dracula basis • Chip Tape-out in accordance with company’s Tape-out Procedure • Positive Attitude Qualifications: • 3+ years Layout experience in Analog and/or Mixed-Signal Circuit Design • Ability to do chip plan, estimate die size and project schedule • Ability to resolve DRC & LVS data verification and tape out chip independently • Familiarity with fundamentals of analog processes • Experience with Cadence and/or VIRTUOSO tools preferable

1.Analog & physical design flow/script development 2.IR/EM sign-off 3.Flip-chip design 4.Physical verification flow

IC layout

1.Analog and mixed mode circuit layout and verification 2.Co-work with designer for layout floor planning,routing and physical verifications 3.command file maintain

1.負責部分全定製版圖的設計和驗證。 2.確保IC佈局符合Circuit Designer設計需求及產品、製程、電氣的規範。

analog and digital circuit layout繪製

Position Description Develop PEGASUS/PVS DRC, FILL, LVS, LPE rule decks and RCX flow for worldwide foundries. Manage onsite technical qualification to ensure both PEGASUS/PVS decks and tools are officially qualified by foundries. Collaborate closely with early adoption customers to track and resolve product issues Establish communication channels with R&D to capture customer needs and requirement spec. Work with R&D to enhance and improve PEGASUS/PVS, positioning it as a leading edge Physical Verification tool Position Requirements B.S. in Electrical Engineering (EE), Computer Science (CS), or related area (or equivalent) and 3 - 5 years of experience with Physical Verification tool support/development OR M.S. in EE or CS, or related area (or equivalent) and 1 - 3 years of experience with Physical Verification tool support/development Profound knowledge with Foundry Design Rules and semiconductor fabrication process Ability to develop PEGASUS/PVS rule deck for worldwide foundries, ensuring quality, performance, and compliance with schedules and qualification requirements. Proficiency in TCL and PERL scripting is required Strong English communication skills. Software development experience preferred; familiarity with Cadence SKILL programming is a plus. Experience with IC design and CAD support is advantageous.

• Responsible for on-time monthly closing and operational reporting package as per management team’s requirements. • Lead the Finance and Accounting (FA) Department by setting goals, defining objectives, and managing team performance. • Oversee daily finance and accounting operations to ensure efficient workflows. • Develop and implement financial strategies, policies, and procedures aligned with the company’s objectives. • Manage the preparation of accurate financial reports to track and reflect operational performance. • Supervise budgeting, financial forecasting, and cash management to maintain sufficient funding and liquidity. • Ensure compliance with legal, regulatory, and tax obligations through timely and accurate filings. • Collaborate with Bora Bio’s senior management team to define financial strategies and manage required documentation. • Optimize financial systems, processes, tools, and internal controls for improved efficiency and accuracy. • Recruit, train, and retain skilled finance and accounting professionals to build a high-performing team. • Manage relationships with partners and stakeholders, including clients, external auditors, and financial institutions • Align financial activities with headquarters (HQ) requests and directives. • Handle and ensure the smooth execution of ad-hoc projects as needed ※職稱及薪資核定將視個人學經歷背景作調整

歡迎2026年畢業並正在找尋研發替代役的同學申請! 職位選擇: Direction 1: Physical Design Engineer Direction 2: ASIC Physical Design Engineer Direction 3: DFX Engineer Direction 4: CAD Tools Development Engineer Direction 5: Design Verification Engineer What you’ll be doing: Key Domains: • Physical and ASIC Design Implementation • Backend and Layout Optimization • Design-for-Excellence (DFX: Test, Manufacturability, Debug) • Development of CAD/EDA Automation Tools • Functional and Formal Design Verification What we need to see: • MS degree from EE/CS or related majors from a prestigious university. • Good knowledge in digital circuit design. • Experience in using Verilog HDL. • Experience in various EDA tools. • Fluent in English reading and writing. • Self-motivated, good team player. Ways to stand out from the crowd: • Proven ability to work independently as well as in a multi-disciplinary group environment • Good command of C/C++ or Verilog programming language. • Familiar with Perl/Python/Tcl/Shell scripting 應徵方式: 請提供以下資料： • 英文個人履歷 • 學士+碩士成績單 (中英文皆可) 提交申請: 請將上述資料投遞至104，符合資格者將會收到進一步的聯繫通知。

1. 熟練Autocad 電腦繪圖操作 2. 具備介面協調討論能力。 3. 其他主管交辦行政事項。

1.數位IP相關功能的設計與實現 2.數位IP仿真與FPGA驗證 3.數位IP/subsys/chip_top的前段整合流程signoff 4.ISO 26262 FMEDA 設計和品質改進 5.與第三方數位 IP 供應商合作