「數位驗證工程師Digital Verification Engineer」的相似工作

⚠️特別說明：此職位需on-site在新竹清大創新育成中心辦公室，無提供遠端工作條件。 ✅About the job • 負責數位IC設計的功能驗證，確保設計符合規格要求。 • 建立UVM驗證平台，撰寫測試案例，進行模組與整合驗證。 • 熟悉AMBA (AXI/AHB/APB) 匯流排協定，應用於驗證環境。 • 使用C語言或SystemVerilog撰寫測試程式，進行功能覆蓋率分析與除錯。 • 與設計團隊，協同解決設計問題。 • 參與測試計畫制定、驗證策略設計及驗證報告撰寫。 ✅基本要求： • 電機、電子、資訊工程相關科系畢業，學士以上學歷。 • 具備3-5年數位IC設計驗證經驗。 • 熟悉AMBA (AXI/AHB/APB) 匯流排協定。 • 熟悉UVM驗證方法學，具備搭建UVM平台經驗。 • 熟悉SystemVerilog或C語言，能撰寫驗證測試程式。 • 熟悉模擬工具 (如VCS、NC-Verilog、ModelSim等)。 • 良好的問題分析與解決能力，具備團隊合作精神。 ✅加分條件： • 具備SoC驗證經驗。 • 熟悉FPGA驗證流程或原型驗證經驗。 • 熟悉低功耗驗證或性能分析經驗。 • 具備腳本開發能力 (Perl、Python、TCL等)。 ✅需具備技能： • AMBA (AXI/AHB/APB) Protocol • UVM驗證方法學(必要) • System Verilog / C 語言 • 功能驗證平台建置 • 模擬工具使用 (VCS / NC-Verilog / ModelSim 等) • 問題分析與除錯能力 • 驗證策略與覆蓋率分析

【工作內容】 • Work with team members and apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market • Provide the technical leadership to the DV team for the project • Work independently on various DV tasks and provide technical guidance to the DV team. • Be involved technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup 【職務條件】 • Master’s degree in Electrical Engineering, Computer Science, or related. • Good understanding of ASIC design verification flow. • RTL coding with Verilog/System Verilog and familiar with front-end design flow and C/C++ programming experiences. • Knowledge of Perl, OVL, SVA, SV, UVM, OVM, script programming, etc. 【其他條件】 • MSEE with a minimum of 5 years, or BSEE with a minimum of 8 years of experience in digital ASIC/SOC design verification • MS/BS degree in EE or CS with expertise in digital IP/SOC design verification.

Develop and maintain environment for SOC pre-silicon verification of: • RTL and netlist simulation • CRV for system fabric • Power-aware simulation • Formal CC and FPV • System level verification with SVA

讓我們跨越國界，千里來相逢，用AI展翅翱翔，來尋找千載難逢的機會 (Tranxform.com 千逢科技) Hardware design verification : • Develop verification environment. • Co-work with hardware designers to verify designs with system verilog and system verilog assertion. • Building, maintaining testbenches and their components using UVM-based methods. • Functional coverage and code coverage. • Generating the random testcases for NPU design,and providing debug reports. • Develop the auto-verifying environment using scripting languages like Perl and Python. Programming Languages: Strong programming skills in languages like System Verilog, Verilog and possibly high-level languages like C/C++. Experience in AI/ML: In-depth knowledge of artificial intelligence and machine learning algorithms. NPU Architecture: Proficiency in designing Neural Processing Unit architectures. Parallel Processing: Understanding of parallel processing and optimization techniques for neural networks. Team Collaboration: Effective communication and collaboration skills within a multidisciplinary team. Problem-solving: Strong analytical and problem-solving skills to address complex design challenges. Knowledge of Industry Trends: Awareness of the latest trends and advancements in NPU technology and AI hardware. Results-Driven: A proactive and results-driven mindset, aiming for high-quality outcomes. Ownership Mentality: Willingness to take ownership and responsibility for the design process. Adaptability: Ability to adapt to evolving technologies and project requirements. Advanced Degree: Typically, a relevant advanced degree (Master's or Ph.D.) in Electrical Engineering, Computer Science, or a related field.

1. Design verification with SystemVerilog/UVM, C/C++ 2. Integration test environment with VIP 3. Develop checker and scoreboard. 4. Verify design with SystemVerilog assertion. 5. Test plan for a verification task. [Requirement] 1. Familiar with SystemVerilog HDL, OOP, Python, TCL, and shell programming. 2. Better to have SoC design and bus concept.

a. Job Description: We are looking for a highly motivated RTL Designer to join our team in developing high-performance digital IPs. The ideal candidate will have experience in Register Transfer Level (RTL) design and verification, with a strong understanding of digital logic, microarchitecture, and ASIC/FPGA development processes. The role involves designing and verifying custom hardware IPs for cutting-edge applications. b. Verification: Develop and execute test plans to verify functionality, performance, and power requirements. Create testbenches using SystemVerilog/UVM for functional verification. Perform simulation, debugging, and root cause analysis for design issues. Conduct code coverage and functional coverage analysis to ensure comprehensive testing. Collaborate with verification and firmware teams to validate IP functionality. c. Qualifications: Bachelor’s/Master’s degree in Electrical Engineering, Computer Engineering, or a related field. 2+ years of experience in RTL design and verification. Proficiency in Verilog, SystemVerilog Strong understanding of digital design concepts, including pipelining, clock domains, and low-power design techniques. Experience with simulation tools (e.g., ModelSim, VCS, Questa) and formal verification techniques. Familiarity with UVM methodology and testbench development. Knowledge of scripting (Python, TCL, Perl, Shell) for automation. Experience with FPGA or ASIC development flows, including synthesis and timing analysis. Strong debugging and problem-solving skills. Excellent communication and teamwork abilities. - Non smoking

## 職務說明 - 應用於無人機雷達系統 - 數位IP架構設計與實作。 - 透過MATLAB/C++協助數位IP驗證 - 透過FPGA整合與驗證。 ## 技能要求 - 具備數位訊號處理經驗 - 具備數位電路設計經驗 - 程式語言必要：Verilog/VHDL, TCL, ##加分條件： - 具備雷達/通訊訊號處理、數位設計架構 - 具備RF/Analog 知識與RF/Analog校準設計 - 程式語言: MATLAB, python, c, c++, Chisel3

1.針對數位電路IP Spec撰寫testcase 與相容性測試 2.有SOC與FPGA前端驗證經驗 3.熟悉數位IC設計流程和相關EDA工具 4.有大型複雜電路或serdes CTRL驗證經驗者尤佳

(a) 負責Tcon IC開發 (b) 負責數位影像處理IP開發 (C) 1.整合使用 FPGA IP，具模擬驗證以達功能的需求 2.系統驗證項目的規劃及系統整合與測試 3.開發、撰寫及驗證 Verilog code (D) 1.使用System Verilog、UVM驗證數位IP 2.依據規格擬定測試計畫並建立隨機測試向量 3.與Design Team密切合作，提高function/code test coverage

## Job Description: - Planning and establishing pass/fail criteria for LEO satellite product testing (e.g., OTA, Thermal Vacuum, Radiation, etc.). - Execution and result analysis of LEO satellite product testing. - Writing test reports and documenting anomalies - Developing and maintaining automated testing programs to improve testing efficiency. ## Skill: - Familiarity with RF or phased array testing is preferred. - Familiarity with Python and basic instrument control is preferred. - Familiarity with military and space testing standards is preferred.

1. Responsible for SOC physical implementation including floorplan, power plan, physical synthesis, clock tree, routing, RC, STA, timing closure, EM/IR, DRC/LVS to GDS out. 2. Responsible for APR physical design flow development & automation

⚠️特別說明：此職位需on-site在新竹清大創新育成中心辦公室，無提供遠端工作條件。 ✅主要職責： 1. 高效能記憶體子系統（DDR/LPDDR Subsystem）之整合、開發與驗證。 2. 參與GenAI SoC設計，包括架構規劃、RTL設計、模擬與驗證。 3. 配合後端設計團隊，進行時序分析與設計優化。 5. 進行設計文件撰寫與維護，確保設計過程符合公司開發流程。 6. 針對客戶需求，進行系統分析與客製化設計開發。 ✅基本要求： 1. 電機、電子、資訊工程相關科系畢業，學士以上學歷。 2. 具備5年以上數位IC設計經驗。 3. 熟悉 DDR PHY 架構、控制器、timing calibration與 training 流程 4. 熟悉SoC Bus Fabric設計，具備AXI、AHB等匯流排介面經驗。 5. 熟悉RTL設計 (Verilog / System Verilog)。 6. 了解前端設計流程，包括模擬、合成、時序分析等。 7. 良好的問題分析能力，具備團隊合作精神。 ✅加分條件： 1. 有參與過 LPDDR Subsystem Integration與Silicon Tape-out 並成功量產 2. 熟悉 Synopsys LPDDR、Cadence GDDR IP/Subsystem 3. 熟悉 UPF、低功耗設計流程 4. 熟悉 DFT 、Scan、BIST ✅ Why Join Us 1. 與頂尖技術團隊共事，參與高效能 AI/高速記憶體解決方案開發 2. 自主創新文化，提供技術發揮與產品影響力兼具的工作環境

Position Description: 1. To provide key technical support in digital IC design implementation product demonstration, and sales presentations. 2. To demonstrate strong ability and to be hands-on in full APR flow including floorplan, placement, timing analysis, CTS, signoff timing closure methodology. 3. To support key customer engagements on the business increase. 4. Have real design tape-out experience especially for advanced node design. 5. To play a leading role among other team members, while receive little instruction on routine and general assignments. Position Requirements: • Master with 10 years working experience or Bachelor with 12+ years’ experience in IC design. (Cadence Innovus experience will be a plus) • Understanding of full APR flow including timing, congestion analysis and low-power methodology. (Experience for Static Timing Analysis, including SI will be plus) • Good communication in English and Chinese, good confidence and good self-motivation. • Be familiar with shell/perl/tcl etc. script language.

【產品範疇】 MOBILE(手持裝置)驅動晶片 【工作內容】 LCD driver(含OLED) Timing Control數位電路的研發設計與驗證 【需求條件】 1.熟悉HDL coding, simulation, synthesis, and STA flow，有量產經驗尤佳 2.熟悉LCD driver(或OLED)規格，具有相關工作經驗尤佳 3.熟悉Timing Control(Global Timing or SRC control timing or GIP timing)數位電路設計，有相關開發經驗者尤佳

由於先進製程與高整合度晶片需要較長的研發時間及高製造成本，DV (Design Verification) 已成為聯發科技晶片開發流程中不可或缺的一環。 CDG DV部門負責開發與執行最高整合度 Smartphone，TV與ASIC驗證工程。 內容包含:整合型驗證環境開發，大數據分析與效能改善，BUS Fabric / EMI (External memory interface ) / Low power functions 驗證規劃及執行。 工作中需要設計及精進Verification plan/methodology/bench，對SOC系統有整體而深入的了解。 利用最新EDA tool and concept來完成你的驗證計畫。 工作地點:新竹/台北

我們專注於3D影像立體雙目視覺技術 產品應用於3D 影像辨識、360 度環景拍照、攝影或AR 與VR 職務內容： ★ USB2.0/3.1或 MIPI 介面之2D/ 3D 影像處理與壓縮之 IC 開發 ★ 影像處理與壓縮相關數位 IP暨產品之開發設計、測試、驗證 條件要求： 1. 對IP Verification, System Verification 有興趣 2. 熟Verilog coding 與 ASIC design Flow 與 Timing Closure 3. 或有 SoC IC 開發經驗 4. 對開發人工智慧((AI) 晶片與邊緣運算有興趣者

【產品範疇】 Mobile/TCON - LCD display driver、OLED display driver Tablet - LCD display driver TV/NB -LCD display driver TCON 產品 【工作內容】 1.DRC/LVS Command file 撰寫&Maintain 2.Laker TF/UDD/PCELL 撰寫 3.PERC rule & 程式的開發 4.Analog design flow development 5.Shell/SKILL/TCL/Python 程式開發 6.新製程廠內的PDK development 7.In house Utility 開發 8.AI 輔助工具的開發與評估

【產品線描述】 Display Timing Controller晶片, 主要負責顯示器的影像最佳化與面板時序驅動, 並具有一MCU系統及完整的色彩/影像處理方案, 得廣泛應用在NB / Monitor / TV / 工控 / 醫療 / 車用 / 公用顯示 【工作說明】 1. 制定IC規格書 2. FPGA 功能驗證及環境架設 3. HW PCB相關設計開發 4. ESD,EMI 問題處理與改善 5. Tooling製作及開發 6. IC 及系統相關驗證 7. FW & SW 開發及驗證 8. IP驗證及相關認證. 9. 支援客戶問題處理 【必要條件】 1. 具備PCB電路設計經驗 2. 具備 IC或FPGA開發驗證相關經驗 3. 對工作細心，有熱忱

【本職缺優先審核至高通官網投遞人選】請至高通官網上傳英文履歷表https://careers.qualcomm.com/careers/job/446706469752 【Talents who apply job through Qualcomm Career Website will be reviewed and considered as top priority】 https://careers.qualcomm.com/careers/job/446706469752 【The Potential Areas To Work Include】 • The main responsibility of this position is to do the performance analysis for world-class snapdragon CPU subsystem for mobile and portable computers. 【Minimum Qualifications】 • Master's, Electrical Engineering, Computer Engineering or Computer Science, emphasizing on computer architecture • Good knowledge on in-order/out-of-order CPU microarchitecture and architecture • Good knowledge on ARM bus protocol • Good knowledge on DDR subsystem • Good in C/C++ and scripting programming • Hands-on experience on performance analysis and validation works 【Preferred Qualifications】 • Experience in benchmark workload characterization and performance bottleneck analysis • Hands-on experience with performance verification on simulator or emulator • Familiar with ARMv8/v9 architecture • Knowledge of OS, firmware and software stacks • Familiar with GCC/LLVM compilation flow

Design CPU functional units. Responsibilities  Defining micro-architecture of the functional units  Writing RTL codes of the functional units  Writing documents of the function units  Working with cross-division teams to resolve functional, performance, power, and frequency issues related to the functional units Qualifications  3+ years of recent experience with Verilog logic design  Knows CPU micro-architecture, e.g. instructions, pipeline, caches, MMU  Knows power consumption of digital circuits  Good communicator in verbal and writing in English