「【AI影像引擎 × ASIC平台設計服務】SoC Design｜DE/DV/PD(CD0000)」的相似工作

1. Architecture design and RTL implementation of Automotive/Smartphone chipset 2. SoC system power and performance analysis 3. SoC system bus and memory subsystem design, integration, and modeling 4. SoC low power design, integration, and modeling 5. SoC functional safety analysis, design, integration, and modeling 6. SoC cyber security analysis, design, integration, and modeling

Responsibilities: • Develop integrated verification environment. • Verify designs with system verilog and system verilog assertion. • Build, maintain and upgrade testbenches and their components using UVM-based methods. • Check functional coverage and code coverage • Create controlled random testcases. Pre-debug and provide debug reports. • Scripting experience using scripting languages like Perl and Python.

我們在尋找具備一定基礎的數位電路前端設計師加入我們的團隊。負責從 RTL 到 Netlist 的完整設計流程，並確保在設計符合市場需求規格的同時，達成高性能、低功耗及面積優化的需求。因此該職位需要了解 IC設計流程，以及業界主流 EDA 工具的實際應用經驗。 工作職責 - 根據設計規格撰寫 RTL - 根據驗證需求建構 verification environment - 執行功能驗證，確保設計的正確性和完整性 - 使用工具生成符合時序、功耗和面積要求的 netlist - 使用工具進行靜態時序分析，確保設計符合時序要求 - 配合前後端工程師，協助完成佈局與布線流程，並確認產出之電路在時序、功耗等方便符合規格 - 分析並解決設計中的時序、功耗及訊號完整性問題

我們專注於3D影像立體雙目視覺技術 產品應用於3D 影像辨識、360 度環景拍照、攝影或AR 與VR 職務內容： ★ USB2.0/3.1或 MIPI 介面之2D/ 3D 影像處理與壓縮之 IC 開發 ★ 影像處理與壓縮相關數位 IP暨產品之開發設計、測試、驗證 條件要求： 1. 對IP Verification, System Verification 有興趣 2. 熟Verilog coding 與 ASIC design Flow 與 Timing Closure 3. 或有 SoC IC 開發經驗 4. 對開發人工智慧((AI) 晶片與邊緣運算有興趣者

Responsible for digital IP coding and micro-architecture design of low-power, high-performance LLM inference accelerators. Drive mapping of lightweight frameworks such as llama.cpp onto NPU, plan compute/memory subsystems, and optimize quantization & KV-cache for production-ready LLM SoCs. Write RTL specs and guide DV plans and P&R convergence for PPA targets. 1. 研讀規格。 2. IC數位邏輯線線路的研發設計。 3. IC數位邏輯線路模擬與合成。 4. FPGA的合成規劃與測試驗證。 5. IC的靜態時序分析 (Static Timing Analysis)。 6. IC佈局後的線路模擬。 7. 撰寫IC規格設計書。 8. IC的除錯與工程變更修改。 9. 協助系統應用部門的進行IC驗證版的規劃。

工作描述 - 跟據系統需求制定硬件架構及硬件功能列表 - 跟架構、物理實現以及芯片驗證團隊一起合作去交付滿足功能/時序/功耗要求的設計，並協助流片前跟流片後的問題分析 - 交付SOC設計項目的RTL/SDC/UPF 設計 崗位要求 - 碩士以上，電機、自動控制、電子、機械相關科系畢業為主 - 具5年以上數位IC設計經驗 - 熟悉CPU 相關的系統設計，協議，以及系統運行的相關行為 - 有實際芯片回來調適、問題分析、性能優化等相關的經驗 - 有高速數字系統相關的設計經驗，能夠運用設計手段去提高運行時脈 - 有DDR/PCIE/USB/UCIE/CXL 相關經驗為佳

The successful candidate will work with team members and apply his/her design techniques to work on different phases of complex logic design for ASIC/SOC project. The role will include working on the following tasks from time to time: HDL coding, documentation, RTL quality check, cooperate with back-end engineer etc. 【Key Responsibilities】 - Responsible for front-end digital logic design in ASIC/SOC projects. - Perform HDL coding (Verilog/SystemVerilog). - Prepare and maintain design documentation (specifications and design documents). - Conduct RTL quality checks (Lint, CDC, power analysis, etc.). - Collaborate with Backend/Physical Design engineers to achieve timing closure. 【Core Requirements】 - Education/Experience: Master’s degree with ≥ 2 years, or Bachelor’s degree with ≥ 3 years of digital ASIC/SOC design experience. - RTL Design: Proficient in RTL coding using Verilog/SystemVerilog or VHDL. - TO / Front-End Flow: Familiar with front-end design flow, including synthesis, Lint, CDC, and STA. - EDA Tools: Experience with tools such as Lint, CDC check, and PrimeTime PX (power analysis). - Documentation: Ability to write design specifications and technical documents. - Collaboration: Work closely with the Design Verification (DV) team on IP verification. 【Preferred Qualifications】 - Familiarity with CPU architectures (x86/ARM/8051). - Knowledge of AMBA bus protocols (AXI/AHB/APB). - Understanding of PCIe protocol.digital IP/SOC design verification.

1. 主動式電子掃描陣列 (相控陣列) 雷達系統之數位控制。 2. 熟悉Verilog與FPGA開發流程，了解High-Level Synthesis開發技術。 3. 具有實作數位訊號處理與數位架構設計於FPGA之經驗。

1.根據通訊演算法，撰寫RTL code (Verilog, VHDL) 2.數位電路設計。 3.承辦及參與委託給業界或學界之研發案。

【工作內容】數位 IC 設計, 包含 Verilog coding, FPGA emulation, IC 驗証 【專業知識技能要求】會 verilog, 有 FPGA 驗證, tapeout 經驗為佳

RTL coding/synthesis/simulation/verification

Design CPU functional units. Responsibilities  Defining micro-architecture of the functional units  Writing RTL codes of the functional units  Writing documents of the function units  Working with cross-division teams to resolve functional, performance, power, and frequency issues related to the functional units Qualifications  Available to start work three months after being hired.  3+ years of recent experience with Verilog logic design  Knows CPU micro-architecture, e.g. instructions, pipeline, caches, MMU  Knows power consumption of digital circuits  Good communicator in verbal and writing in English

This is a good opportunity to join a startup company working in UWB and Radar product. Co-work with ASIC design team for product development competive salary and startup package 工作內容: - 協助 Radar 定位演算法DSP實現及其驗證 - 協助數位晶片Serial介面(I2C/SPI)開發 - 協助產品驅動程式開發和相關測試 具備條件: - 具3年以上Digital IC design或FPGA開發相關經驗 - 熟悉RTL coding、simulation & synthesis流程及其開發工具使用 - 具C/C++ coding 和 debug 能力 - 能理解基礎數位運算原理如FIR IIR cordic佳

1. Layout & Plan UI: Cowork with UI/UX Team to fit customer requirements. 2. Integration and Development: Use and modify proprietary framework to integrate AI models into production and ensure smooth deployment to customer requirements. 3. Documentation & Maintenance: Document stuff(processes/algorithms/results) for sharing and maintain commitments of projects.

1. 數位設計電路開發與維護。 2. SoC系統設計電路開發與維護。 3. 數位設計與晶片系統設計技術諮詢。 4. 其它主管交辦事項。

Job Description : • Design optimized digital blocks meeting functional, cost and low power constraints and ensure spec compliance. • Cover digital backend design from synthesis, upf, static timing analysis and logic equivalent checking. • Interface with P&R for digital hand-off and post layout verification. • Collaboration with analog engineers and test engineers on analog testability design and debugging. • Work closely with Application/GUI team in FPGA prototype and lab debugging. • Perform physical silicon device evaluation where necessary. Qualifications : • 8+ years of experience in ASIC/IC design with deep knowledge of whole IC design flow from RTL coding, synthesis, static timing analysis, logic equivalent checking to post-layout checking. • Experience in DFT or physical design is a plus. • Experience in FPGA prototype and lab equipment and lab debug is a plus. • Fluent in either Verilog RTL coding and ASIC design methodology. • Competence in developing design constraints for synthesis, STA and P&R handoff. • Ability to work both independently and part of a team. • Excellent interpersonal, organizational and communications skills.

We are seeking a highly motivated Design Verification Engineer to join our dynamic team. You will be responsible for ensuring the functional correctness of complex digital designs using industry-leading verification methodologies such as UVM, Formal Verification, and Coverage-Driven Verification. 【Key Responsibilities】 · Develop detailed verification plans based on design specifications and architectural documents. · Build and maintain System Verilog UVM-based testbenches for SoC/Subsystem/IP-level verification. · Write constrained-random and directed test cases to validate functionality, performance, and corner-case scenarios. · Perform coverage analysis (functional coverage, code coverage, assertions coverage) and drive towards coverage closure. · Apply Formal Verification techniques (e.g., property checking, connectivity checking) where applicable. · Support simulation regression runs and maintain automation scripts (Perl/Python/TCL/Makefile). · Participate in design and verification reviews, providing valuable feedback to improve quality.

a. Job Description: We are looking for a highly motivated RTL Designer to join our team in developing high-performance digital IPs. The ideal candidate will have experience in Register Transfer Level (RTL) design and verification, with a strong understanding of digital logic, microarchitecture, and ASIC/FPGA development processes. The role involves designing and verifying custom hardware IPs for cutting-edge applications. b. Verification: Develop and execute test plans to verify functionality, performance, and power requirements. Create testbenches using SystemVerilog/UVM for functional verification. Perform simulation, debugging, and root cause analysis for design issues. Conduct code coverage and functional coverage analysis to ensure comprehensive testing. Collaborate with verification and firmware teams to validate IP functionality. c. Qualifications: Bachelor’s/Master’s degree in Electrical Engineering, Computer Engineering, or a related field. 2+ years of experience in RTL design and verification. Proficiency in Verilog, SystemVerilog Strong understanding of digital design concepts, including pipelining, clock domains, and low-power design techniques. Experience with simulation tools (e.g., ModelSim, VCS, Questa) and formal verification techniques. Familiarity with UVM methodology and testbench development. Knowledge of scripting (Python, TCL, Perl, Shell) for automation. Experience with FPGA or ASIC development flows, including synthesis and timing analysis. Strong debugging and problem-solving skills. Excellent communication and teamwork abilities. - Non smoking

1. 光通訊產品相關高速介面數位設計 (112G PAM4 SerDes) 2. 依據系統規格, 執行架構設計以及撰寫硬體描述語言 (RTL) 3. 具有高速介面, 低功耗, 以及D/A混合電路設計經驗者尤佳

1. Work on 3~7nm design implementation, methodology, and sign-off 2. Perform synthesis, DFT, floorplan, clock planning, place and route, timing closure, ECO, IR signoff, and physical verification 3. Manage schedule, resolve design and flow issues, drive methodologies and execution