「Sr. Logic Design Engineer(竹北)」的相似工作

ASIC design engineer responsible for post-RTL design flow. He/She will be responsible for block and /or chip level synthesis, timing closure, DFT generation, and ECOs. The responsibilities include but are not limited to. •    Improve the design methodology and flow. •    Synthesis, timing closure, and DFT support for various types of SerDes IPs ranging from 10Gbps to 224Gbps data rates for different applications. •    Collaborate with Analog/Digital design teams to deliver competitive SerDes IP solutions for all the Marvell product lines. •    Provide support to the product teams, for both pre and post-silicon

Job Description: Microchip’s Wireless Solutions Group is seeking a FPGA engineer to support SOC development for our next generation, mixed signal, wireless products. The role will focus on the areas of RTL design, FPGA synthesis and FPGA system bring-up, debug and validation. It will require a proactive candidate with a proven record of success in cross functional and cross site team environments. Key Responsibilities: • Collaborate with the design team to develop and optimize the RTL for FPGA , ensuring its efficiency and functionality. • Conduct FPGA synthesis using industry-standard tools to transform RTL code into a target FPGA device. • Assist in the initial bring-up of the FPGA system, ensuring proper functionality and identifying and resolving any issues that may arise. • Perform through testing and validation of the SOC design, both at the RTL level and in the FPGA implementation, and resolve any bugs or issues that are discovered. • Collaborate closely with the FW (Firmware), Validation, and RF teams to successfully carry out FPGA system bring-up, debug, and validation activities.

Introduction to the job Do you like challenges and do you want to work in a fast pacing supply chain environment to support some of the biggest semiconductor companies worldwide? Are you familiar with Logistics Operations and like to managing urgent demands on a daily basis?  If this sounds like you and if you have a strong customer oriented mindset, here is your mission. Role and responsibilities For our Global Operations Center in Taiwan we are searching for Supply Chain Professionals. You fulfill the demand of our customers for spare parts and tools for their maintenance activities on some of the most complex machines in the right quantity and at the right time & cost. Time is of the essence to ensure a seamless production of our customers without interruptions on our machines. -Handling of urgent material requests from worldwide customers in a rolling 24/7 shift system with the right customer focus, while meeting all milestones related to communication and execution -Monitoring of worldwide shipments  -Ability to resolve complex issues and drive improvements to further optimize processes -Ability to support escalations and provide communication proposals for review -Constructive and reliable communication with worldwide stakeholders from all departments within ASML -This position requires shift work. Education and Experience Bachelor's Degree in related subject i.e. Supply Chain Management, Information Science, Engineering etc. preferred -Minimum 1 year of relevant experience in an international company, semiconductor industry is preferred -A tactical thinker with strong interpersonal and communication skills -Analytical thinking and ability to organize and prioritize workload Skills Working at the cutting edge of tech, you’ll always have new challenges and new problems to solve – and working together is the only way to do that. You won’t work in a silo. Instead, you’ll be part of a creative, dynamic work environment where you’ll collaborate with supportive colleagues.  There is always space for creative and unique points of view. You’ll have the flexibility and trust to choose how best to tackle tasks and solve problems. To thrive in this job, you’ll need the following skills: -Stress-resistant; act under high pressure -Flexible; willing to go the extra mile for the customer -Excellent professional communication in English, written and oral -Drive for results; does not stop until solution has been found, even when obstacles arise -Team player -Change management competencies -Convincing, pro-active and “can do” mentality -Cultural awareness -Experience with ERP system(s), SAP R/3 knowledge preferred -Ability to prioritize Diversity and inclusion ASML is an Equal Opportunity Employer that values and respects the importance of a diverse and inclusive workforce. It is the policy of the company to recruit, hire, train and promote persons in all job titles without regard to race, color, religion, sex, age, national origin, veteran status, disability, sexual orientation, or gender identity. We recognize that diversity and inclusion is a driving force in the success of our company. Need to know more about applying for a job at ASML? Read our frequently asked questions.

As senior/staff digital design engineer, this person is required to support all digital design activities on company products, design services as well as internal IP development. Below are the responsibilities: - Responsible for RTL Design and writing of test bench - experience in IP core design such as peripheral interfaces, CPU cores, digital controllers - Architecture review, RTL design, functional verification, post synthesis simulations. - Responsible for SOC system Integration & verification - Experience in SoC Architecture and Microarchitecture A - Experience in ARM CPU integration to SoC - Experience in SDRAM Memory Controller integration - Experience in interconnect matrix, AHB Bus Arbitration, multi-layer AHB Bus architecture - Experience in SoC Peripherals design: GPIO, RTC, UART, I2C, I2S, and SPI - Excellent in Verilog RTL coding and simulation - Familiar with FPGA prototype and verification - SD/SDIO relative experience is an added advantage. - AMBA Interface relative experience is an added advantage. - Knowledge in controller design (USB, PCIe, SATA, and Ethernet) is an added advantage. - Preferably done some FPGA prototyping in previous employment Desired Skills & Competency Requirement: - Verilog RTL coding - SoC design flow and SoC peripheral IP design - FPGA prototyping and emulation - System validation and verification - Characterization and the handling of test equipment - Digital front-end design, simulation and synthesis - Verification in system Verilog OVM - Low power synthesis methodology - Digital support on DFT and ATPG - Scripting in Perl, Python, TCL, UNIX, Linux

1. SOC/IP 整合工作，從RTL到 Netlist 2. clock tree structure design 3. Lint / CDC check / Synthesis/ DFT/ LEC

我們在尋找具備一定基礎的數位電路前端設計師加入我們的團隊。負責從 RTL 到 Netlist 的完整設計流程，並確保在設計符合市場需求規格的同時，達成高性能、低功耗及面積優化的需求。因此該職位需要了解 IC設計流程，以及業界主流 EDA 工具的實際應用經驗。 工作職責 - 根據設計規格撰寫 RTL - 根據驗證需求建構 verification environment - 執行功能驗證，確保設計的正確性和完整性 - 使用工具生成符合時序、功耗和面積要求的 netlist - 使用工具進行靜態時序分析，確保設計符合時序要求 - 配合前後端工程師，協助完成佈局與布線流程，並確認產出之電路在時序、功耗等方便符合規格 - 分析並解決設計中的時序、功耗及訊號完整性問題

1. 支援計畫功能與系統驗證與除錯。 2. 規劃及協調驗證資源、項目及時程。 3. 與Hardware engineer 溝通設計FPGA硬體架構規劃 4. 與Software engineer 溝通設計FPGA 控制介面 5. SoC FPGA系統整合。 6. 演算法之RTL實現或IP整合、獨立撰寫 Testbench & Debug FPGA電路 7.高速介面(HDMI/eDP/3G-SDI/12G-SDI)、DDR、I2C、UART、SPI等介面整合應用 8. 具醫療影像及色彩處理開發

我們專注於打造次世代電路模擬專用硬體加速器，誠徵數位IC設計師，加入我們的行列，透過數位電路設計與驗證實力，推動電路模擬的極致效能與可靠性。 你將負責： ▪️ 設計電力分析專用晶片架構及系統 ▪️ RTL設計與功能驗證，確保系統正確性與效能表現 ▪️ 參與SoC數位區塊的功能設計、整合與驗證 ▪️ 進行綜合、時序分析與低功耗設計優化 我們期待你具備： ▪️ 電子/電機工程學士以上學歷 ▪️ 精通Verilog/SystemVerilog與RTL設計流程 ▪️ 熟悉綜合與時序分析方法 ▪️ 具備DSP演算法硬體實現經驗 ▪️ 理解低功耗設計技術與實務 專業工具： ▪️ Synopsys Design Compiler ▪️ Cadence Genus ▪️ Mentor Graphics 加分條件： ▪️ 具備完整SoC設計專案經驗 ▪️ 熟悉UVM或其他驗證方法學 ▪️ 有28nm以下先進製程設計或量產經驗 ▪️ 具備電力電子或電源管理電路相關背景 如果你熱愛透過數位IC設計挑戰能源晶片的極限，歡迎加入我們，打造更智慧的硬體未來！

Responsible for digital IP coding and micro-architecture design of low-power, high-performance LLM inference accelerators. Drive mapping of lightweight frameworks such as llama.cpp onto NPU, plan compute/memory subsystems, and optimize quantization & KV-cache for production-ready LLM SoCs. Write RTL specs and guide DV plans and P&R convergence for PPA targets. 1. 研讀規格。 2. IC數位邏輯線線路的研發設計。 3. IC數位邏輯線路模擬與合成。 4. FPGA的合成規劃與測試驗證。 5. IC的靜態時序分析 (Static Timing Analysis)。 6. IC佈局後的線路模擬。 7. 撰寫IC規格設計書。 8. IC的除錯與工程變更修改。 9. 協助系統應用部門的進行IC驗證版的規劃。

## 職務說明 - 應用於無人機雷達系統 - 數位IP架構設計與實作。 - 透過MATLAB/C++協助數位IP驗證 - 透過FPGA整合與驗證。 ## 技能要求 - 具備數位訊號處理經驗 - 具備數位電路設計經驗 - 程式語言必要：Verilog/VHDL, TCL, ##加分條件： - 具備雷達/通訊訊號處理、數位設計架構 - 具備RF/Analog 知識與RF/Analog校準設計 - 程式語言: MATLAB, python, c, c++, Chisel3

1. IC產品之研發與應用設計 2. 建立IC產品基礎規格並設計IC電路 3. 降低產品成本，提高IC品質，支援軟/硬體開發 4. 熟數位IC設計及相關工具 Verilog HDL、Cadence IES simulator 、FPGA tools、Synopsys DC

- 用Verilog/SystemVerilog撰寫RTL，負責數位電路介面與模擬驗證。 - 參與晶片模組整合與ASIC合成（含DFT、時序收斂）到Tape-out。 - 主導設計專案與SoC整合。 - 帶領小團隊（3人），負責任務分配與技術指導。

Job Title: NPU Modeling Engineer Job Description: Overview: We are seeking an experienced NPU Architect to join our team. As an NPU Architect, you will play a crucial role in designing and implementing the hardware model for our Neural Processing Unit. Your expertise will be instrumental in ensuring efficient and accurate execution of neural network workloads on our NPU. Responsibilities: 1. NPU Architecture Design: • Collaborate with cross-functional teams to define the architecture and specifications for the NPU. • Design the NPU's core components, including the PE array, memory hierarchy, and control logic. • Optimize for performance, power efficiency, and scalability. 2. Bit-True Hardware Model Implementation: • Develop a bit-true hardware model of the NPU in C language. • Ensure that the model accurately represents the NPU's behavior, including arithmetic operations, memory access, and control flow. • Validate the model against reference neural network workloads. 3. Cycle-Accurate Modeling: • Create a cycle-accurate model of the NPU to simulate its behavior at the clock cycle level. • Account for pipeline stages, data dependencies, and timing constraints. • Use tools like Verilog, system-Verilog, or specialized simulation environments to achieve cycle-accurate modeling. 4. Performance Analysis and Optimization: • Profile the NPU model to identify bottlenecks and areas for improvement. • Propose and implement optimizations to enhance performance and reduce latency. • Collaborate with software teams to fine-tune the NPU's behavior. 5. Verification and Validation: • Create testbenches and test vectors to validate both the bit-true and cycle-accurate models. • Conduct functional and performance testing to ensure correctness and compliance with specifications. • Debug and resolve any discrepancies between the models and the actual NPU. 6. Documentation and Communication: • Document the NPU architecture, design decisions, and implementation details. • Present findings, progress, and challenges to stakeholders and management. • Collaborate with software engineers, firmware developers, and system architects. Qualifications: • Master's or Ph.D. degree in Electrical Engineering, Computer Science, or a related field. • Minimum of 3 years of experience in NPU architecture design and implementation. • Proficiency in C/C++/Verilog/System-Verilog programming for hardware modeling. • Familiarity with systolic arrays, matrix multiplication, and neural network accelerators. • Knowledge of bit-true modeling, fixed-point arithmetic, and floating-point arithmetic. • Experience with verification tools and simulation environments. • Strong analytical and problem-solving skills. • Excellent communication and teamwork abilities. • Attention to detail and commitment to quality. If you are passionate about NPU architecture, hardware modeling, and want to be part of a team driving innovation, we encourage you to apply. Join us in shaping the future of AI!

公司財會部門特色： - 集團IPO公司，作業內容與規範與上市櫃公司相同 - 集團主要財會功能建置於台灣，會計人員統籌集團各子公司帳務處理． - 會計人員皆為會計系所畢業，並多數具有事務所工作經驗 - 公司文化尊重個人生活，少加班需求，讓員工工作與生活兼顧． ERP系統：公司目前使用Oracle Netsuites 雲端ERP系統 配合事務所：資誠聯合會計師事務所 配合證券承銷商：中國信託證券 工作內容：(會計專員) 該職務的主要工作是子公司的帳務處理： ＊主要工作包含子公司整體帳務工作，並完成編製相關報表.　 * 負責帳務以外，該分公司銀行相關財務性工作 * 配合會計師查帳準備必要性資料 其他附屬工作：財會相關專案工作或主管交辦事項 人員能力需求： 1. 會計帳務獨立運作 2. 會計商學相關科系畢業 3. 需要2年以上會計相關工作經驗（會計師事務所工作尤佳） 4. 獨立成熟，並足夠與內部同仁與外部單位溝通能力，

1. Algorithm/Spec to RTL design, verification and synthesis 2. IP FPGA verification 3. Stardand IP configuration, integration and verification 4. Whole chip/Subsystem IP Integration and verification

About us: VICI Holdings' Hardware team is seeking a skilled FPGA Engineer to join our dynamic group. In this role, you will be pivotal in advancing our trading systems, contributing to the development and enhancement of cutting-edge technologies. We boast the leading software development team in Taiwan and possess FPGA design technology in parallel with wall street trading firms. This expertise enables us to build low-latency, fully automated trading systems. Our trading strategies cover stocks, futures, and derivatives, achieving a daily global trading volume in the hundreds of millions dollars. Roles/ Responsibilities: • High speed IP interface design (such as PCIE gen 3, 4 / Ethernet, DDR etc.) • In charge of FPGA design/ implementation/simulation. • Transmission protocol layer development. • Optimizing hardware for latency. • Proficiency with Xilinx design environment. Candidate Requirements: • BS/MS degree above from EE, CE with 2+ years of relevant work experience • Experience in high-speed interface design or knowledge in PCIE/ Ethernet/MIPI/DDR design or implementation is a plus • Experience using System Verilog and at least two prior RTL design is a required. • Demonstrated ability to tackle complex design challenges and implement effective solutions Other Requirements: • High self-motivated individual with good communication skill. • English level – working level proficiency is a plus. Interview Process: • Resume selection ->Coding Test -> AI Interview (Online) -> F2F Interview -> HR Manager

● 開發與整合AI SoC核心模組（如記憶體與資料傳輸控制器）。 ● 設計高效匯流排架構，優化模組間資料傳輸性能。 ● 執行RTL設計、模擬與驗證，確保功能與時序符合要求。 ● 協助後端團隊進行時序分析與設計優化。 ● 撰寫技術文件，遵循高標準開發流程。

1. 有TDDI IC開發經驗, AFE/DSP/MCU 開發經驗者 2. 有IC串接與MCU協同架構開發經驗者 3. 有開發TFT-LCD面板相關時序控制器經驗者 4. 有數位訊號經驗與通訊原理者尤嘉

■工作內容： 眼鏡銷售，商品管理及上架。 專業驗光配鏡，眼鏡加工製作及售後服務。 店鋪一般事務 : ＊有調派海外國家的機會。 ■工作待遇 ： 國家考試合格驗光生：月薪 NT45,000元 。(含證照津貼8,000元) 國家考試合格驗光師：月薪 NT47,000元 。(含證照津貼10,000元) 滿足綁所資格 (師/生條件)，並實際擔任驗光所負責人者：月薪NT53,000(師)/51,000(生) ※新竹以北(含)地區驗光師／生人員，通過社內考核，提供北區津貼NT3,000元/月。 ■上班時間＆休假： 勤務時間8小時+休息時間1小時。 月休9~10天。(遇國定假日調移排休) ■社內研修： 提供社內基本技術課程研修。 賣場訓練課程。 針對驗光師法提供特別研修課程。 (以上皆為上班時間上課) ■未來職涯發展： 我們提供自主性升遷制度，想要晉升至管理階層或總公司職位的夥伴， 皆可透過 [選舉制度]、[社內FA制度]往自己想從事的職位邁進。 ■雙向面談制度： 在OWNDAYS約半年一次，希望者全體可申請與直屬區主管直接對談， 可直接向直屬主管提出自己希望的待遇、薪資、條件等想法。 ■社員獎勵旅行 : 成績優秀者（門市・推薦者）將可獲得國內外旅遊獎勵。 (每回舉辦地點皆有所不同) 獎勵旅遊的目的就是盡情的大玩特玩！

負責數位IP演算法, 與數位工程師共同開發影像處理電路