「數位IC設計工程師(晶片整合)」的相似工作

The successful candidate will work with team members and apply his/her design techniques to work on different phases of complex logic design for ASIC/SOC project. The role will include working on the following tasks from time to time: HDL coding, documentation, RTL quality check, cooperate with back-end engineer etc. 【Key Responsibilities】 - Responsible for front-end digital logic design in ASIC/SOC projects. - Perform HDL coding (Verilog/SystemVerilog). - Prepare and maintain design documentation (specifications and design documents). - Conduct RTL quality checks (Lint, CDC, power analysis, etc.). - Collaborate with Backend/Physical Design engineers to achieve timing closure. 【Core Requirements】 - Education/Experience: Master’s degree with ≥ 2 years, or Bachelor’s degree with ≥ 3 years of digital ASIC/SOC design experience. - RTL Design: Proficient in RTL coding using Verilog/SystemVerilog or VHDL. - TO / Front-End Flow: Familiar with front-end design flow, including synthesis, Lint, CDC, and STA. - EDA Tools: Experience with tools such as Lint, CDC check, and PrimeTime PX (power analysis). - Documentation: Ability to write design specifications and technical documents. - Collaboration: Work closely with the Design Verification (DV) team on IP verification. 【Preferred Qualifications】 - Familiarity with CPU architectures (x86/ARM/8051). - Knowledge of AMBA bus protocols (AXI/AHB/APB). - Understanding of PCIe protocol.digital IP/SOC design verification.

1.根據通訊演算法，撰寫RTL code (Verilog, VHDL) 2.數位電路設計。 3.承辦及參與委託給業界或學界之研發案。

我們專注於3D影像立體雙目視覺技術 產品應用於3D 影像辨識、360 度環景拍照、攝影或AR 與VR 職務內容： ★ USB2.0/3.1或 MIPI 介面之2D/ 3D 影像處理與壓縮之 IC 開發 ★ 影像處理與壓縮相關數位 IP暨產品之開發設計、測試、驗證 條件要求： 1. 對IP Verification, System Verification 有興趣 2. 熟Verilog coding 與 ASIC design Flow 與 Timing Closure 3. 或有 SoC IC 開發經驗 4. 對開發人工智慧((AI) 晶片與邊緣運算有興趣者

About us: VICI Holdings' Hardware team is seeking a skilled FPGA Engineer to join our dynamic group. In this role, you will be pivotal in advancing our trading systems, contributing to the development and enhancement of cutting-edge technologies. We boast the leading software development team in Taiwan and possess FPGA design technology in parallel with wall street trading firms. This expertise enables us to build low-latency, fully automated trading systems. Our trading strategies cover stocks, futures, and derivatives, achieving a daily global trading volume in the hundreds of millions dollars. Roles/ Responsibilities: • High speed IP interface design (such as PCIE gen 3, 4 / Ethernet, DDR etc.) • In charge of FPGA design/ implementation/simulation. • Transmission protocol layer development. • Optimizing hardware for latency. • Proficiency with Xilinx design environment. Candidate Requirements: • BS/MS degree above from EE, CE with 2+ years of relevant work experience • Experience in high-speed interface design or knowledge in PCIE/ Ethernet/MIPI/DDR design or implementation is a plus • Experience using System Verilog and at least two prior RTL design is a required. • Demonstrated ability to tackle complex design challenges and implement effective solutions Other Requirements: • High self-motivated individual with good communication skill. • English level – working level proficiency is a plus. Interview Process: • Resume selection ->Coding Test -> AI Interview (Online) -> F2F Interview -> HR Manager

DRAM數位邏輯電路設計 『具工作經驗者，薪資另議』

【About Us】 VICI Holdings' Hardware team is seeking a Senior Digital Design Engineer to join our dynamic group. In this role, you will be pivotal in advancing our trading systems, contributing to the development and enhancement of cutting-edge technologies. We boast the leading digital hardware development team in Taiwan and possess FPGA design technology in parallel with wall street trading firms. This expertise enables us to build ultra-low-latency, fully automated trading systems. Our trading strategies cover stocks, futures, and derivatives, achieving a daily global trading volume in the hundreds of millions dollars. 【Roles/ Responsibilities】 • Micro-architecture, design and implement high-performance digital circuits optimized for low-latency application • Develop high speed data paths, ensuring minimal logic depth and efficient pipeline • Optimize critical paths and combinational logic to reduce propagation delays and improve throughput • Work with Verilog/ SystemVerilog to implement RTL design • Apply parallelism and resource sharing techniques to enhance performance and throughput • Develop latency-aware micro-architectures for real-time processing and networking applications • Debug, optimize and iterate on designs using FPGA platform and cycle-accurate simulation • Work closely with digital/system verification engineers to ensure functional correctness and performance validation • Take ownership of FPGA verification tasks to ensure design correctness and performance. • Develop and execute verification plans for high-speed IPs such as PCIe, Ethernet, and Switches. • Support system validation engineer to debug FPGA issue Design Collaboration: • Collaborate closely with Algorithm, software, design validation and application team to define micro-architecture Performance Analysis: • Conduct performance testing and analysis, ensuring the low-latency goals are met across various use cases. • Capability to solve routing timing issue and analysis FPGA timing report result. 【Candidate Requirements】 • Master’s degree or above in EE, CE, or CS, plus 3–8 years of high-speed digital-design experience • Hands-on experience in IP-level digital-circuit design or IP integration (preferred) • Proficient in debugging and optimization with VCS and Verdi simulation tools • Comfortable working in Linux/Unix environments • Strong analytical and problem-solving skills with a performance-driven mindset 【Other Requirements】 • Proven ability to solve complex design challenges and deliver robust solutions • Experience designing ultra-low-latency data paths—arithmetic units, multiplexers, FIFOs, registers—for high-performance applications (preferred) • Familiarity with FPGA verification tools such as Quartus or Vivado (a plus) • Knowledge of high-bandwidth memory interfaces (DDR, HBM, etc.) • Understanding of networking protocols (Ethernet, PCIe, etc.) 【Interview Process】 • Resume Screening → HR Phone Screen → Face-to-Face Interview (with 30-60mins on-site coding test)

ASIC design engineer responsible for post-RTL design flow. He/She will be responsible for block and /or chip level synthesis, timing closure, DFT generation, and ECOs. The responsibilities include but are not limited to. •    Improve the design methodology and flow. •    Synthesis, timing closure, and DFT support for various types of SerDes IPs ranging from 10Gbps to 224Gbps data rates for different applications. •    Collaborate with Analog/Digital design teams to deliver competitive SerDes IP solutions for all the Marvell product lines. •    Provide support to the product teams, for both pre and post-silicon

[Responsibilities] ★ Experienced in ISP (Image Signal Processing) ★ Plan design architecture. ★ Develop high quality digital design. ★ Be familiar with IC design flow. [Minimum Qualifications] ★ Outstanding problem analysis and debugging skills. ★ Experienced in C language. ★ Experienced in Verilog RTL language ★ Experienced in digital IC design front-end flow ★ Experienced in CAD tool usage such as simulation tool, linting tool, synthesis tool, member compiler [Preferred Qualifications] ★ Nice to have experiences in scripting language. ★ Nice to have experiences in FPGA flow

1. 主動式電子掃描陣列 (相控陣列) 雷達系統之數位控制。 2. 熟悉Verilog與FPGA開發流程，了解High-Level Synthesis開發技術。 3. 具有實作數位訊號處理與數位架構設計於FPGA之經驗。

The Staff/Sr. Engineer, CPLD will be based in Taiwan Taipei Wugu Site. The Staff/Sr. Engineer, CPLD performs the responsibility for CPLD programming and validation in Server/Storage Projects request. What a typical day looks like: 1. Skilled FPGA/CPLD Design Engineer with strong capabilities in Server/Storage system and hardware-level design. 2. Responsible for development and integration of CPLD/FPGA that implement functionality on prototypes: spanning from low-level hardware sequence control, logic control & status for embedded systems, to high-speed links, to high level IP blocks, to custom hardware-accelerated algorithms & filters. 3. Work closely with Hardware, BIOS, BMC and Firmware team for CPLD/FPGA development. 4. Designing validation plan and development spec. 5. Debugging platform and systems issues. The experience we are looking to add to our team: 1. 3-10 years of working experience in Firmware development. 2. Familiar in Verilog RTL language. Experienced with CPLD/FPGA development on Lattice, Altera and Xilinx devices. 3. Experience with I2C, SPI, LPC, UART, PCIe protocol design 4. Experience with verification methodologies, RTL and gate level simulations and debug. 5.Good problem-solving skills. The information we collect: We may collect personal information that you choose to submit to us through the Website or otherwise provide to us. This may include your contact details; information provided in online questionnaires, feedback forms, or applications for employment; and information you provide such as CV/Resume. We will use your information for legitimate business purposes such as responding to comments or queries or answering questions; progressing applications for employment; allowing you to choose to share web content with others or; where you represent one of our customers or suppliers, administering the business relationship with that customer or supplier.

我們專注於打造次世代電路模擬專用硬體加速器，誠徵數位IC設計師，加入我們的行列，透過數位電路設計與驗證實力，推動電路模擬的極致效能與可靠性。 你將負責： ▪️ 設計電力分析專用晶片架構及系統 ▪️ RTL設計與功能驗證，確保系統正確性與效能表現 ▪️ 參與SoC數位區塊的功能設計、整合與驗證 ▪️ 進行綜合、時序分析與低功耗設計優化 我們期待你具備： ▪️ 電子/電機工程學士以上學歷 ▪️ 精通Verilog/SystemVerilog與RTL設計流程 ▪️ 熟悉綜合與時序分析方法 ▪️ 具備DSP演算法硬體實現經驗 ▪️ 理解低功耗設計技術與實務 專業工具： ▪️ Synopsys Design Compiler ▪️ Cadence Genus ▪️ Mentor Graphics 加分條件： ▪️ 具備完整SoC設計專案經驗 ▪️ 熟悉UVM或其他驗證方法學 ▪️ 有28nm以下先進製程設計或量產經驗 ▪️ 具備電力電子或電源管理電路相關背景 如果你熱愛透過數位IC設計挑戰能源晶片的極限，歡迎加入我們，打造更智慧的硬體未來！

想找一個能真正發揮實力、與頂尖團隊共同打造未來技術的平台嗎？ 在芯鼎，我們結合 AI 與影像處理技術，開發具突破性的SoC解決方案，應用於自動駕駛、無人機、機器人、AI 與高效能運算等前沿領域。我們以 ARM 架構（基於 ARM Compute Sub-System & SystemReady）為基礎，打造引領未來的先進視覺以及 AI SoC 設計平台。 在這裡，你將有機會： 與資深工程師與跨域團隊合作，挑戰技術極限 深入 AI 系統與 SoC 架構設計，推動產業升級與創新 從 SoC 微架構、設計實作到驗證流程，全面提升技術視野與實戰能力 無論你擅長或有興趣領域 ，是 IC 設計（DE）、驗證開發（DV），先進製程晶片實體設計含前後端優化以及可測試性設計（Physical design ，DFT）。 我們誠摯邀請你加入芯鼎，與我們一起打造改變世界的設計架構平台！ ***最終職稱與職級將依學經歷與專長核定*** 【SoC 平台、IP 整合】職責與技能(3年以上專業經驗) 1. 規劃與實作 SoC 系統架構，執行模組功能驗證與整體平台驗證 2. 整合並驗證各類高速介面與標準 IP，包括：ARM 架構、UCIe、PCIe、DDR、Ethernet、USB、MIPI TX/RX、eDP、Security Engine 等 加分技能： 1. 熟悉晶片開發全流程，涵蓋前端 RTL 設計、驗證，到後端實作與收斂 2. 具備跨模組與跨部門協同整合經驗，能有效推動系統級平台建構與整合效率 【Design Verification (DV)】職責與技能(3年以上專業經驗) 1. 建立並維護模組與系統層級的驗證環境 2. 使用 SystemVerilog 撰寫測試平台，進行功能驗證與模擬分析 3. 撰寫並整合 SystemVerilog Assertions（SVA）以提升驗證覆蓋率與錯誤檢出能力 必要技能： 1. 精通 UVM（Universal Verification Methodology）驗證方法學 2. 熟悉 AMBA 協定（AXI、AHB、APB 等）之功能與驗證應用 3. 熟悉硬體驗證平台，如 Synopsys HAPS, Synopsys ZeBu，具備實際部署或加速驗證經驗者尤佳 【PD/Design for Testability (DFT)】職責與技能(3年以上專業經驗) 1. 實作區塊與整合等級的可測試性設計（包含 DC/AC Scan、Boundary Scan (BSD)、MBIST 與 Repair） 2. 撰寫與維護 DFT 模式下的 SDC，協助 APR 與前端設計團隊完成時序收斂 3. 執行 RTL 等級的綜合（synthesis），並配合 DFT 架構需求整合設計流程 必要技能： 1. 熟悉 Synopsys 或 Mentor 的 DFT 工具與完整設計流程 2. 熟悉 UPF (Unified Power Format) 與 Synopsys 綜合工具（如 Design Compiler） 3. 具備 Scan Stitch、MBIST 修補、自動測試向量生成等相關經驗者優先

A. 負責高階投影機FPGA開發 B. 承接 FPGA (XILINX/ALTERA) 設計 C. 數位電路設計、驗證與模擬 D. 影像系統或數位影像處理演算法設計與實現

1.影像應用或訊號處理 IC 研發 2.對數位影像、訊號處理, Verilog/VHDL, 具FPGA design flow 經驗。

1. USB3.0 host/device開發驗證相關工作 2. RTL coding/synthesis/simulation/verification

1.RTC Module/ IP design. 2.Design synthesis. 3.Design verification. 4.DFT/ siemens tools.

1. 熟Verilog及C/C++語言設計。 2. 規劃執行產品韌體之撰寫。 3. 執行、協助或配合韌體新技術之研發、導入。 4. 執行產品韌體測試。

[job description] Wolley is seeking candidates for a digital design engineer position. You will join an experienced team designing next-generation memory, storage controllers, and high-speed interface standard. You will also contribute to design concept discussion, architecture definition, as well as design implementation. ‧ Architecture design and RTL implementation ‧ System bus and related peripheral designs ‧ SoC and emulation platform design ‧ SoC system performance analysis [Requirement] 1. Bachelor's or Master's degree in Electrical Engineering or related fields 2. Familiar with RTL design, SystemVerilog, front-end design flow 3. The following working knowledge is desired: * Python programming * TCL scripting * Universal Verification Methodology (UVM) * Low power design and analysis

【工作內容】 1. 數位電路邏輯控制程式設計 2. 基本通訊界面控制 (UART/I2C/SPGIO/SPI) 3. CPLD規格評估 4. CPLD規格書規劃、撰寫、維護 5. Verilog/VHDL模擬除錯設計 6. CPLD測試、除錯、驗證及最佳化 7. 維護現有CPLD專案 【其他條件&加分項目】 1. 熟悉 Verilog, 2. 若具有 Altera Quartus II, Lattice Diamond , Modelsim能力佳 3. 具有開創性及解決問題的能力 4. 客戶導向及良好溝通技巧 5. 具備推動團隊完成任務的能力 6. 流程管理能力

Design CPU functional units. Responsibilities  Defining micro-architecture of the functional units  Writing RTL codes of the functional units  Writing documents of the function units  Working with cross-division teams to resolve functional, performance, power, and frequency issues related to the functional units Qualifications  Available to start work three months after being hired.  3+ years of recent experience with Verilog logic design  Knows CPU micro-architecture, e.g. instructions, pipeline, caches, MMU  Knows power consumption of digital circuits  Good communicator in verbal and writing in English