「SoC/ASIC/IP digital design engineer」的相似工作

負責數位IP演算法, 與數位工程師共同開發影像處理電路

This vacancy is open for talent pool collection. We will contact you if we have proper vacancies that fit with your profile. Job Mission Represent manufacturing and act as gatekeeper from manufacturing to D&E function Add value in overall manufacturing processes such as forming, machining, joining, and assembling Job Description Contribute to the solution of faults and takes the necessary initiatives and practical decisions to ensure zero repeat Identify gaps and drive assigned process improvement projects and successful delivery Initiate and drive new procedure changes and projects Develop and maintain networks across several functional stakeholders Prioritize works and projects based on business situation Transfer knowledge and train colleagues on existing and newly introduced products Education Master degree in technical domain (e.g. electrical engineering, mechanical engineering, mechatronics) Experience 3-5 years working experience in design engineering Personal skills Show responsibility for the result of work Show proactive attitude and willing to take initiative Drive for continuous improvement Able to think outside of standard processes Able to work independently Able to co-work with different functional stakeholders Able to demonstrate leadership skills Able to work in a multi-disciplinary team within a high tech(proto) environment Able to think and act within general policies across department levels Diversity and inclusion ASML is an Equal Opportunity Employer that values and respects the importance of a diverse and inclusive workforce. It is the policy of the company to recruit, hire, train and promote persons in all job titles without regard to race, color, religion, sex, age, national origin, veteran status, disability, sexual orientation, or gender identity. We recognize that diversity and inclusion is a driving force in the success of our company. Need to know more about applying for a job at ASML? Read our frequently asked questions.

1.負責影像處理設計及架構 2.了解ASIC Flow及獨立作業 3.能擔任專案負責人

1. Participate in digital design specification, architecture definition, and microarchitecture planning. 2. Conduct FPGA prototyping, testing, and debugging of digital IP designs. 3. Collaborate closely with analog/mixed-signal design teams, firmware engineers, and system engineers to ensure successful product integration. 4. Develop, implement, and verify RTL code (Verilog/SystemVerilog) for high-speed Serdes interfaces including USB, DP, HDMI, DDR and PCIe.

負責IP開發、整合與偵錯 -- 利用Verilog/SystemC從事邏輯設計與數位系統設計，以相關自動化軟體進行電路合成及模擬驗證，並配合利用FPGA系統平台進行系統整合與測試驗證。

1. SerDes CTRL IP RTL 開發與維護 (例如LPDDR､UFS､NAND Controller...) 2. 設計驗證 3. FPGA相關設計與實作 以上工作依個人意願酌情分配

1.Work with team members and apply design techniques to work on different phases of complex logic design for ASIC/SOC project. 2. Working on the following tasks from time to time: HDL coding, documentation, RTL quality check, cooperate with back-end engineer etc.

數位IC設計

Job Description: Are you ready to push the boundaries of what's possible in technology? Join the trailblazers at Sandisk. As a Principal Engineer you will be at the forefront of designing high-performance SoCs for storage solutions. By leveraging your expertise in RTL design and modern tools like GitHub Copilot, you will enhance the design process and productivity. You will collaborate with cross-functional teams to deliver groundbreaking solutions that meet our high standards of quality and performance. Key Responsibilities: • Innovate, implement, and verify RTL code for complex ASICs. • Performed design tasks across various design stages. • Utilize advanced AI-driven tools, including GitHub Copilot, to streamline the design process. • Collaborate with hardware and software teams for seamless integration. • Provide mentorship to junior engineers. • Stay abreast of the latest industry trends and emerging technologies in AI and ASIC design. Qualifications: • Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field. • Hands-on experience in digital IP/SoC design: minimum 7 years with a Bachelor's degree, or 6 years with a Master’s degree. • Proven experience in ASIC RTL design, with a strong grasp of Verilog/System Verilog. • Familiarity with the whole digital design flow. • Proficiency in leveraging AI tools, including GitHub Copilot, for design and development. • Strong problem-solving skills and the ability to thrive in a dynamic environment. • Excellent communication and teamwork abilities. Preferred Qualifications: • Experience in low-power design techniques and methodologies. • Familiarity with high-speed interfaces (e.g., SD Express, Compact Flash, PCIe, DDR). • Proficiency in scripting languages (e.g., Python, TCL) for automation. About Sandisk: Sandisk, a leader in data storage solutions, is seeking talented and experienced ASIC RTL Design Engineers to join our cutting-edge team. Our mission is to revolutionize the data storage industry through relentless innovation and technology breakthroughs.

1. 實作開發TFT-LCD面板相關時序控制器 2. functions、algorithm相關 3. 對MOBILE(手持裝置)驅動晶片的數位IC設計工作有興趣者 4. 觸控IC、TDDI或指紋辨識IC開發經驗 5. MCU或DSP IC開發經驗 6. 工作地點：此職缺在【台南(樹谷園區)、新竹】皆設有相關單位，可依需求選擇工作地點

【在華邦，學習不設限，讓AI技術力與你的未來力同步成長!】 我們深信「人才永續」是企業創新的核心動能。華邦持續投資於數據素養與AI應用的培育，支持每一位人才掌握AI與數據應用的核心能力。 ．內部學習平台提供超過4,000堂線上課程，其中包含近850堂資料科學、人工智慧、數據思維與程式技術等多元主題，支援彈性自主學習 ．建立跨部門的 AI實作班與技術社群，定期舉辦研習與交流活動，讓知識轉化為實戰力 ．完善數據應用學習資源，結合資料呈現(Power BI、Tableau)、資料處理(Python、JMP)、流程自動化(Power Automate、UiPath)、AI助手(Copilot)，協助同仁有效以數據驅動決策與創新。 ．搭配專業語言學習平台，提供學習補助與資源，鼓勵同仁持續進修，拓展國際視野 無論你是技術新秀還是資深專才，華邦鼓勵所有領域都能與AI結合，與國際接軌。持續精進、突破自我！ 【邀請您將104履歷同步上傳至華邦官方網站，將使您的履歷優先被主管看見】此職缺履歷登錄網址:https://bit.ly/4lHkbzD [工作內容] 1. Responsible for design and development of digital ICs, including Verilog RTL coding, functional verification, and optimization. 2. Participate in the complete ASIC design flow: specification, RTL design, synthesis, static timing analysis, and physical design handoff. 3. Perform Design-for-Test (DFT) implementation, including scan insertion and MBIST, to support manufacturability and testability. 4. Support SoC integration, including bus protocols (AMBA) and high-speed interfaces (PCIe, SerDes).

The successful candidate shall possess the capability to design and analyze high speed, high performance analog / mixed signal circuits, including data converters, PLLs, and SERDES, in advanced CMOS FinFET technologies. She or he shall bring the design all the way to production. Imagine being part of a team that is fundamentally changing the way people communicate, the way they collaborate, the way they watch TV and explore the universe through the internet. Utilizing our uniquely differentiated technology, we have created an Intelligent Transport Network with more speed, capacity and scalability than ever before. Imagine a world with unlimited bandwidth. The network of tomorrow will allow for content and creativity limited only by the imaginations of its users. If this is something that interests you, that excites you, come take a look at a team not bound by large company obstacles and bureaucracy, where an idea today can be set in motion tomorrow. Come take a look at Infinera! Engaging in the high-speed analog circuit design, you have the chance to create the technical differentiation for Infinera to hold the market leadership. We together will revolutionize the era of efficient high speed transmission by building the cutting-edge circuitry. Your Key Responsibilities Would Include: Design, implement, and simulate the functionality and performance of various high-speed analog circuits, including the ADCs and DACs; Create the layout floor plans to optimize the overall performance; Supervise the layout activities and give concise guidelines to layout engineers, need to be hands on in drawing layout if necessary; Exploring the trade-offs of the different topologies and propose the best solution to achieve or exceed the requirements in terms of power/area/linearity/bandwidth, etc. Develop the analog testing plans and work with the PE/TE teams to characterize the functionality and performance of the products to ensure the quality; Need to support and comply with the team’s design methodologies and release flows. Mandatory Knowledge/Skills/Abilities: Must be extremely familiar with essential CAD tools, such as Cadence Virtuoso, Spectre, Incisive, Calibre, EMX, and Totem EM/IR, etc. Must have a proven tracking record of designing complex analog / mixed signal IPs or chips in deep submicron CMOS technologies. Must have experiences in bringing high performance analog IPs including but not limited to high-speed ADC, high-speed DAC, and high-frequency low-jitter PLL to production. Must have a decent understanding in CMOS analog / mixed signal design methodologies and circuit analysis; Must have a good understanding of device physics and the impacts of layout effects; Able to perform the behavioral modeling the blocks and circuits with Verilog-A or Verilog-AMS; Collaborative with other local or remote team members in a fast-paced professional environment. Preferred Knowledge/Skill/Abilities: Fluent in verbal and written communications; Independently resolves issues and conquer design challenges; Self-motivated and detail-oriented; Has the knowledge of (optical) communication theories and Matlab coding. Education and Experience Requirements: Minimum Requirement for Principal Design Engineer: M.S. in E.E. with 12+ years’ experience, or Ph.D. in E.E. with 8+ years’ experience

Job Title: NPU Modeling Engineer Job Description: Overview: We are seeking an experienced NPU Architect to join our team. As an NPU Architect, you will play a crucial role in designing and implementing the hardware model for our Neural Processing Unit. Your expertise will be instrumental in ensuring efficient and accurate execution of neural network workloads on our NPU. Responsibilities: 1. NPU Architecture Design: • Collaborate with cross-functional teams to define the architecture and specifications for the NPU. • Design the NPU's core components, including the PE array, memory hierarchy, and control logic. • Optimize for performance, power efficiency, and scalability. 2. Bit-True Hardware Model Implementation: • Develop a bit-true hardware model of the NPU in C language. • Ensure that the model accurately represents the NPU's behavior, including arithmetic operations, memory access, and control flow. • Validate the model against reference neural network workloads. 3. Cycle-Accurate Modeling: • Create a cycle-accurate model of the NPU to simulate its behavior at the clock cycle level. • Account for pipeline stages, data dependencies, and timing constraints. • Use tools like Verilog, system-Verilog, or specialized simulation environments to achieve cycle-accurate modeling. 4. Performance Analysis and Optimization: • Profile the NPU model to identify bottlenecks and areas for improvement. • Propose and implement optimizations to enhance performance and reduce latency. • Collaborate with software teams to fine-tune the NPU's behavior. 5. Verification and Validation: • Create testbenches and test vectors to validate both the bit-true and cycle-accurate models. • Conduct functional and performance testing to ensure correctness and compliance with specifications. • Debug and resolve any discrepancies between the models and the actual NPU. 6. Documentation and Communication: • Document the NPU architecture, design decisions, and implementation details. • Present findings, progress, and challenges to stakeholders and management. • Collaborate with software engineers, firmware developers, and system architects. Qualifications: • Master's or Ph.D. degree in Electrical Engineering, Computer Science, or a related field. • Minimum of 3 years of experience in NPU architecture design and implementation. • Proficiency in C/C++/Verilog/System-Verilog programming for hardware modeling. • Familiarity with systolic arrays, matrix multiplication, and neural network accelerators. • Knowledge of bit-true modeling, fixed-point arithmetic, and floating-point arithmetic. • Experience with verification tools and simulation environments. • Strong analytical and problem-solving skills. • Excellent communication and teamwork abilities. • Attention to detail and commitment to quality. If you are passionate about NPU architecture, hardware modeling, and want to be part of a team driving innovation, we encourage you to apply. Join us in shaping the future of AI!

1. Design verification with SystemVerilog/UVM, C/C++ 2. Integration test environment with VIP 3. Develop checker and scoreboard. 4. Verify design with SystemVerilog assertion. 5. Test plan for a verification task. [Requirement] 1. Familiar with SystemVerilog HDL, OOP, Python, TCL, and shell programming. 2. Better to have SoC design and bus concept.

## 職務說明 - 應用於無人機雷達系統 - 數位IP架構設計與實作。 - 透過MATLAB/C++協助數位IP驗證 - 透過FPGA整合與驗證。 ## 技能要求 - 具備數位訊號處理經驗 - 具備數位電路設計經驗 - 程式語言必要：Verilog/VHDL, TCL, ##加分條件： - 具備雷達/通訊訊號處理、數位設計架構 - 具備RF/Analog 知識與RF/Analog校準設計 - 程式語言: MATLAB, python, c, c++, Chisel3

1. Speech/LCD 相關 ASIC 設計開發 2. IC spec訂定討論 (含 analog IP spec) 3. 數位電路設計、整合及 Back-end flow 4. 跨部門 IC 驗證 5. 協助處理良率及客訴問題

Product : OLED DDI 1. Develop integrated verification environment. 2. Verify designs with system verilog and system verilog assertion. 3. Develop and optimize verification flow and methodology. 4. Good knowledge of IC design flow. 5. Scripting experience using scripting languages like Perl and Python.

★系統單晶片設計助理工程師 1. 協助執行IC設計前端相關的數位合成 (Tool: Fusion Compiler, Genus) 2. 利用C相關程式優化工作流程 => 同下 3. 協助開發IC => 利用C語言,tcl script工作流程自動化,讓tools自動撈相關report及執行好分析 4. QC => 跑LEC tools確認synthesis合成與RTL是對的 5. C語言 => 須具備寫程式的能力,像基本資料分類,或寫出數學運算公式,利用程式語言方便做大量資料分析 6. 執行STA分析 (Tool: PrimeTime) 7. 協助整理及分析各項report ★ IC 實體設計助理工程師(APR) 1. 在區塊層級的實體實作中進行 R2G（Ready to GDS）流程。 2. 協助進行 DRC（設計規則檢查）/LVS（佈局與電路比對）/ANT（天線效應）/ERC（電氣規則檢查）驗證。 3. 協助 EM（電遷移）/IR（電壓降）結果修正。 4. 負責先進製程（2nm/3nm/4nm）的 Netlist-to-GDS（從電路網表至最終佈局圖）流程： a. 使用 Innovus 完成 floorplan、preCTS、postCTS、postRoute 各階段： 　i. 檢查 floorplan 品質，包括電源架構、SRAM 擺放、端點填充元件（endcap cells）、接地井元件（welltap cells）、電源開關元件（power switch cells）等。 　ii. 檢查 preCTS 階段品質，包括壅塞/溢出情況、元件密度、設定時間違規（setup violation）、漏電比率（leakage ratio）。 　iii. 檢查 postCTS 階段品質，包括壅塞/溢出情況、元件密度、設定/保持時間違規（setup/hold violations）、漏電比率。 　iv. 檢查 postRoute 階段品質，包括 DRC、金屬短路、設定/保持時間違規、漏電比率。 b. 檢查 IR 違規報告並修正： 　i. 分析 IR 違規原因，包括靜態 IR、動態 IR、電源 EMI、訊號 EMI。 　ii. 修正這些違規的方法。 c. 檢查 DRC/LVS 報告並修正： 　i. 分析實體驗證違規原因，包括 DRC、LVS、ANT。 　ii. 修正這些違規的方法。 ★ 員工福利 獎金與補助：提供年終獎金、三節禮金，午餐與晚餐費補助。 保險制度：完善的團體保險保障。 工作氛圍：穩定合作的工作環境，重視員工學習與成長。 員工關懷：定期舉辦員工聚餐與交流活動，增進團隊凝聚力。"

我們正在尋找像你這樣的初級冒險者，一起加入我們的開發旅程！ 我們是一間成立於日出之國帝都下町提供全面向服務的公司 從攝影、居家清潔、垃圾處理到 IT 開發，我們涉獵廣泛，擁抱各種可能 而「IT」，只是我們冒險世界中的一個分支。 現在，我們開放新手招募中！ 不需要華麗技能、不需擁有傳說裝備， 只要你有熱情、有好奇心，願意學、願意改、願意嘗試失敗，我們願意一起升等。 不中途採用，因為想培養成公司的形狀。 第二新卒可考慮。

1. 負責IC佈局和佈線的設計和開發 2. 實現佈局和佈線的細節設計和調整 3. 與相關的團隊成員合作，確保佈局和佈線設計能夠達到高效率和性能 4. 配合其他工程師進行相關的測試、分析和報告 5. 解決相關佈局和佈線問題 6. 修改維護 Command file 7. 使用CADENCE VIRTUOSO或LAKER等工具進行IC佈局和佈線的驗證