「數位IC設計資深工程師( Logic IC Design Senior Engineer)」的相似工作

The successful candidate will work with team members and apply his/her design techniques to work on different phases of complex logic design for ASIC/SOC project. The role will include working on the following tasks from time to time: HDL coding, documentation, RTL quality check, cooperate with back-end engineer etc. 【Key Responsibilities】 - Responsible for front-end digital logic design in ASIC/SOC projects. - Perform HDL coding (Verilog/SystemVerilog). - Prepare and maintain design documentation (specifications and design documents). - Conduct RTL quality checks (Lint, CDC, power analysis, etc.). - Collaborate with Backend/Physical Design engineers to achieve timing closure. 【Core Requirements】 - Education/Experience: Master’s degree with ≥ 2 years, or Bachelor’s degree with ≥ 3 years of digital ASIC/SOC design experience. - RTL Design: Proficient in RTL coding using Verilog/SystemVerilog or VHDL. - TO / Front-End Flow: Familiar with front-end design flow, including synthesis, Lint, CDC, and STA. - EDA Tools: Experience with tools such as Lint, CDC check, and PrimeTime PX (power analysis). - Documentation: Ability to write design specifications and technical documents. - Collaboration: Work closely with the Design Verification (DV) team on IP verification. 【Preferred Qualifications】 - Familiarity with CPU architectures (x86/ARM/8051). - Knowledge of AMBA bus protocols (AXI/AHB/APB). - Understanding of PCIe protocol.digital IP/SOC design verification.

1. 主動式電子掃描陣列 (相控陣列) 雷達系統之數位控制。 2. 熟悉Verilog與FPGA開發流程，了解High-Level Synthesis開發技術。 3. 具有實作數位訊號處理與數位架構設計於FPGA之經驗。

About us: VICI Holdings' Hardware team is seeking a skilled FPGA Engineer to join our dynamic group. In this role, you will be pivotal in advancing our trading systems, contributing to the development and enhancement of cutting-edge technologies. We boast the leading software development team in Taiwan and possess FPGA design technology in parallel with wall street trading firms. This expertise enables us to build low-latency, fully automated trading systems. Our trading strategies cover stocks, futures, and derivatives, achieving a daily global trading volume in the hundreds of millions dollars. Roles/ Responsibilities: • High speed IP interface design (such as PCIE gen 3, 4 / Ethernet, DDR etc.) • In charge of FPGA design/ implementation/simulation. • Transmission protocol layer development. • Optimizing hardware for latency. • Proficiency with Xilinx design environment. Candidate Requirements: • BS/MS degree above from EE, CE with 2+ years of relevant work experience • Experience in high-speed interface design or knowledge in PCIE/ Ethernet/MIPI/DDR design or implementation is a plus • Experience using System Verilog and at least two prior RTL design is a required. • Demonstrated ability to tackle complex design challenges and implement effective solutions Other Requirements: • High self-motivated individual with good communication skill. • English level – working level proficiency is a plus. Interview Process: • Resume selection ->Coding Test -> AI Interview (Online) -> F2F Interview -> HR Manager

1. Participate in digital design specification, architecture definition, and microarchitecture planning. 2. Conduct FPGA prototyping, testing, and debugging of digital IP designs. 3. Collaborate closely with analog/mixed-signal design teams, firmware engineers, and system engineers to ensure successful product integration. 4. Develop, implement, and verify RTL code (Verilog/SystemVerilog) for high-speed Serdes interfaces including USB, DP, HDMI, DDR and PCIe.

1. 具 0~2年數位晶片設計，或有 0~5年類比晶片設計工作經驗。 2. 具備基本數位和類比電路知識，熟習標準晶片設計流程。 3. 熟習業界常用EDA tools, 或Matlab/ Simulink。 4. 研習過CMOS or BiCMOS 類比設計電路課程，對放大器有基礎認識。 5. Experience in these areas is preferred： * BiCMOS or CMOS high-speed (>20Gb/s) circuit, Linear electrical amplifier & equalizer, High-speed (>25G) CDR/PLL/SerDes. * Linear optical laser driver & receiver (TIA + linear amplifier) 本職位負責類比IC電路的設計、驗證和除錯。這是一個高度技術性的職位，對公司的產品開發至關重要。我們正在尋找一位熱愛類比IC設計並具有相關經驗的人才，以推動公司的技術創新和發展。 如果您對這個職位感興趣，請投遞您的履歷表，我們立即與您聯繫。

【工作內容】 • Work with team members and apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market • Provide the technical leadership to the DV team for the project • Work independently on various DV tasks and provide technical guidance to the DV team. • Be involved technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup 【職務條件】 • Master’s degree in Electrical Engineering, Computer Science, or related. • Good understanding of ASIC design verification flow. • RTL coding with Verilog/System Verilog and familiar with front-end design flow and C/C++ programming experiences. • Knowledge of Perl, OVL, SVA, SV, UVM, OVM, script programming, etc. 【其他條件】 • MSEE with a minimum of 5 years, or BSEE with a minimum of 8 years of experience in digital ASIC/SOC design verification • MS/BS degree in EE or CS with expertise in digital IP/SOC design verification.

Responsibilities: • Develop integrated verification environment. • Verify designs with system verilog and system verilog assertion. • Build, maintain and upgrade testbenches and their components using UVM-based methods. • Check functional coverage and code coverage • Create controlled random testcases. Pre-debug and provide debug reports. • Scripting experience using scripting languages like Perl and Python.

我們專注於打造次世代電路模擬專用硬體加速器，誠徵數位IC設計師，加入我們的行列，透過數位電路設計與驗證實力，推動電路模擬的極致效能與可靠性。 你將負責： ▪️ 設計電力分析專用晶片架構及系統 ▪️ RTL設計與功能驗證，確保系統正確性與效能表現 ▪️ 參與SoC數位區塊的功能設計、整合與驗證 ▪️ 進行綜合、時序分析與低功耗設計優化 我們期待你具備： ▪️ 電子/電機工程學士以上學歷 ▪️ 精通Verilog/SystemVerilog與RTL設計流程 ▪️ 熟悉綜合與時序分析方法 ▪️ 具備DSP演算法硬體實現經驗 ▪️ 理解低功耗設計技術與實務 專業工具： ▪️ Synopsys Design Compiler ▪️ Cadence Genus ▪️ Mentor Graphics 加分條件： ▪️ 具備完整SoC設計專案經驗 ▪️ 熟悉UVM或其他驗證方法學 ▪️ 有28nm以下先進製程設計或量產經驗 ▪️ 具備電力電子或電源管理電路相關背景 如果你熱愛透過數位IC設計挑戰能源晶片的極限，歡迎加入我們，打造更智慧的硬體未來！

## 職務說明 - 應用於無人機雷達系統 - 數位IP架構設計與實作。 - 透過MATLAB/C++協助數位IP驗證 - 透過FPGA整合與驗證。 ## 技能要求 - 具備數位訊號處理經驗 - 具備數位電路設計經驗 - 程式語言必要：Verilog/VHDL, TCL, ##加分條件： - 具備雷達/通訊訊號處理、數位設計架構 - 具備RF/Analog 知識與RF/Analog校準設計 - 程式語言: MATLAB, python, c, c++, Chisel3

1. Architecture design and RTL implementation of Automotive/Smartphone chipset 2. SoC system power and performance analysis 3. SoC system bus and memory subsystem design, integration, and modeling 4. SoC low power design, integration, and modeling 5. SoC functional safety analysis, design, integration, and modeling 6. SoC cyber security analysis, design, integration, and modeling

ASIC design engineer responsible for post-RTL design flow. He/She will be responsible for block and /or chip level synthesis, timing closure, DFT generation, and ECOs. The responsibilities include but are not limited to. •    Improve the design methodology and flow. •    Synthesis, timing closure, and DFT support for various types of SerDes IPs ranging from 10Gbps to 224Gbps data rates for different applications. •    Collaborate with Analog/Digital design teams to deliver competitive SerDes IP solutions for all the Marvell product lines. •    Provide support to the product teams, for both pre and post-silicon

Design CPU functional units. Responsibilities  Defining micro-architecture of the functional units  Writing RTL codes of the functional units  Writing documents of the function units  Working with cross-division teams to resolve functional, performance, power, and frequency issues related to the functional units Qualifications  Available to start work three months after being hired.  3+ years of recent experience with Verilog logic design  Knows CPU micro-architecture, e.g. instructions, pipeline, caches, MMU  Knows power consumption of digital circuits  Good communicator in verbal and writing in English

1. 主FPGA與CPLD專案開發與維護 2. 熟RTL coding, 具Xilinx ISE/Vivado或Altera Quartus II專案設計經驗 3. 能與軟,韌,硬體等相關部門co-work 4. 具Xilinx PCIe 與 MIG DDR3/4系統整合經驗者佳

1.根據通訊演算法，撰寫RTL code (Verilog, VHDL) 2.數位電路設計。 3.承辦及參與委託給業界或學界之研發案。

Job Description We are seeking a highly skilled ASIC Verification Engineer to join our team in Chupei, Taiwan. In this role, you will be responsible for developing and implementing comprehensive verification strategies for complex ASIC designs, ensuring the highest quality and reliability of our semiconductor products. Develop and execute verification plans for complex ASIC designs Create and maintain testbenches using SystemVerilog and UVM Design and implement efficient verification environments Perform functional and formal verification of digital designs Develop automated test scripts to improve verification efficiency Analyze and debug design issues identified during verification Collaborate with design engineers to resolve functional discrepancies Generate detailed verification reports and documentation Stay updated with industry trends and emerging verification methodologies Contribute to the continuous improvement of verification processes and tools Qualifications Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field 5+ years of experience in ASIC verification with strong proficiency in SystemVerilog and UVM Experience with Verilog, VHDL, and industry-standard simulation tools (e.g., Synopsys VCS, Cadence Xcelium) Experience of CPU, GPU, NPU or HBM verification Knowledge of formal verification techniques and tools Strong debugging, problem-solving, and analytical skills Solid understanding of digital logic design, computer architecture, and communication protocols Excellent organizational skills with strong attention to detail Good communication and teamwork skills in a fast-paced environment

※ Job Contents: 1. DDR/HBM controller IP design 2. DDR/HBM IP customer support 3. Execute digital IP front-end flow ※ Requirements: 1. 3-years digital IC design experiences 2. Senior/Technical Manager: 8-years digital IC design experiences 3. Familiar with DDR protocol is a plus 4. Familiar with AMBA interface is a plus 5. Familiar with IC front-end design flow such as Lint/CDC, Synthesis, LEC/formality, PrimeTime STA is a plus

1. SerDes CTRL IP RTL 開發與維護 (例如LPDDR､UFS､NAND Controller...) 2. 設計驗證 3. FPGA相關設計與實作 以上工作依個人意願酌情分配

【產品範疇】 MOBILE(手持裝置)驅動晶片 【工作內容】 LCD driver(含OLED) Timing Control數位電路的研發設計與驗證 【需求條件】 1.熟悉HDL coding, simulation, synthesis, and STA flow，有量產經驗尤佳 2.熟悉LCD driver(或OLED)規格，具有相關工作經驗尤佳 3.熟悉Timing Control(Global Timing or SRC control timing or GIP timing)數位電路設計，有相關開發經驗者尤佳

Job Description: In this position the individual will develop test environment, test plan, and test cases based on the product specification and related industrial standards. The individual will require initiating a test plan review with the team and updating the test plan accordingly. The candidate will require executing and developing the test cases based on test plan, debugging and reporting the test result to achieve full function coverage goal. The individual will require developing ASIC bench functional test programs and doing ASIC bring-up and ASIC bench testing. The ideal individual must have proven ability to achieve results in a fast moving, dynamic environment. The candidate must have ability to coordinate priorities and initiatives and clear communication skill.

讓我們跨越國界，千里來相逢，用AI展翅翱翔，來尋找千載難逢的機會 (Tranxform.com 千逢科技) Hardware design verification : • Develop verification environment. • Co-work with hardware designers to verify designs with system verilog and system verilog assertion. • Building, maintaining testbenches and their components using UVM-based methods. • Functional coverage and code coverage. • Generating the random testcases for NPU design,and providing debug reports. • Develop the auto-verifying environment using scripting languages like Perl and Python. Programming Languages: Strong programming skills in languages like System Verilog, Verilog and possibly high-level languages like C/C++. Experience in AI/ML: In-depth knowledge of artificial intelligence and machine learning algorithms. NPU Architecture: Proficiency in designing Neural Processing Unit architectures. Parallel Processing: Understanding of parallel processing and optimization techniques for neural networks. Team Collaboration: Effective communication and collaboration skills within a multidisciplinary team. Problem-solving: Strong analytical and problem-solving skills to address complex design challenges. Knowledge of Industry Trends: Awareness of the latest trends and advancements in NPU technology and AI hardware. Results-Driven: A proactive and results-driven mindset, aiming for high-quality outcomes. Ownership Mentality: Willingness to take ownership and responsibility for the design process. Adaptability: Ability to adapt to evolving technologies and project requirements. Advanced Degree: Typically, a relevant advanced degree (Master's or Ph.D.) in Electrical Engineering, Computer Science, or a related field.