「智原科技子公司- MCU I/O電路設計工程師」的相似工作

1.IO電路維護 或 ESD設計開發。 2.未來協助高壓元件及 IC ESD Plan 規劃。 3.未來訓練具維護簡易類比設計Analog Circuit IP 能力。 4.具獨立作業能力、態度積極主動並能協調Plan 規劃事務。

******以下有兩個不同的職位****** 【Analog IC Designer (DRAM IO) - 竹北】 工作內容 1. IO 設計. 2. DDR RX/TX 設計. 3. DDR 類比. 4. 擁有 DRAM IO 設計經驗，有 DDR5 以上經驗者尤佳。 擅長工具: HSPICE、Python、Laker、ADP、Custom Compiler 1. 學習過電子學、電磁學、電路學、工程數學等基本課程且成績優良。 2. Familiar with Analog Circuit Design 【 Analog IC Designer (Integration) - 竹北】 工作內容 1. Analog IP top integration, including projects of SSD/UFS/eMMC/SD 等。 2. 基本類比電路設計概念，例如 LDO、DCDC、BANDGAP、Voltage Detector 或 PLL、ADC 等。 3. 協助故障樣品分析與 IC 測試。 其他條件 1. 熟悉量產相關知識與經驗者佳。 2. 類比設計經驗超過 3 年。

We are looking for a proactive and challenge-driven engineer to join our memory design team. This role primarily focuses on gate-level simulation and functional verification to ensure product quality and alignment with specifications. 【Key Responsibilities】 1. Memory circuit design and verification. 2. Gate-level verilog simulation against to the datasheet. 3. Failure mode analysis. 【Qualifications】 1. Experience in SRAM, DRAM, or other memory product design. 2. Solid understanding of digital circuit design and Verilog HDL. 3. Experience with simulation and debugging, able to work independently. 4. Hands-on experience in failure mode analysis is a plus. 5. Deep RTL design experience is not required, but strong gate-level simulation and verification skills are essential.

記憶體Receiver 和 OCD (I/O 電路) 設計

1. 產線靜電防護(ESD)量測計畫制定與執行 2. 靜電防護測試與分析結果判讀 3. 客戶問題處理與溝通 4. 生產線直接人員作業流程檢視與教育訓練‧ 5. 生產線稽核、6S稽核檢視及改善 6. 協助主管異常調查與改善

【工作職責 (Responsibilities)】： ★ Build & innovate on high-speed analog/mixed-signal circuits such as PCIe/DDR/HDMI... transmitter and receiver in deep sub-micron CMOS technology for integration in SoC products. ★ Work with digital team on specification definition ★ Create behavior model for analog/digital evaluation ★ Compliance test for SerDes IP 【符合條件 (Qualifications)】： ★ Familiar with high speed SerDes specification ★ Familiar with IC/SoC design flow ★ Familiar with analog simulation flow ★ Experience SerDes analog blocks design ★ Must be good team player 【必須條件 (Minimum Qualifications)】： ★ Familiar with Audio analog IP design, such as Preamp/DAC/ADC (including SAR and DSM) 【優秀條件 (Preferred Qualifications)】： ★ Familiar with controller integration ★ Familiar with other baseband analog IP design, such as BGAP/LDO/XTAL/PLL, etc. ★ Familiar with ESD, Latch up, I/O ★ Familiar with layout flow

Job desicription: Our Design Team specializes in the challenging field of Non-Volatile Memory (NVM) IC circuit design. We are actively seeking an experienced Analog Circuit Design Engineer to contribute to our cutting-edge developments in embedded NVM solutions and surrounding circuitry. As a key member of our team, you will be responsible for the design, verification, and debugging of essential analog building blocks like Bandgap references, LDOs, and Charge Pumps. A significant part of your role will involve designing critical memory peripheral circuits for NVM IP and test chips, including Array interfaces, Decoding logic, and Sense Amplifiers. Your responsibilities will span the design lifecycle, from contributing to IP specifications and core circuit design to ensuring performance through layout optimization and comprehensive corner simulations of NVM IPs. We are looking for candidates with proven expertise in analog circuit design, ideally with prior experience in embedded memory or NVM technologies. If you are an experienced analog designer eager to tackle complex challenges in non-volatile memory, we encourage you to apply and help shape the future of memory technology.

This vacancy is open for talent pool collection. We will contact you if we have proper vacancies that fit with your profile. Job Mission Represent manufacturing and act as gatekeeper from manufacturing to D&E function Add value in overall manufacturing processes such as forming, machining, joining, and assembling Job Description Contribute to the solution of faults and takes the necessary initiatives and practical decisions to ensure zero repeat Identify gaps and drive assigned process improvement projects and successful delivery Initiate and drive new procedure changes and projects Develop and maintain networks across several functional stakeholders Prioritize works and projects based on business situation Transfer knowledge and train colleagues on existing and newly introduced products Education Master degree in technical domain (e.g. electrical engineering, mechanical engineering, mechatronics) Experience 3-5 years working experience in design engineering Personal skills Show responsibility for the result of work Show proactive attitude and willing to take initiative Drive for continuous improvement Able to think outside of standard processes Able to work independently Able to co-work with different functional stakeholders Able to demonstrate leadership skills Able to work in a multi-disciplinary team within a high tech(proto) environment Able to think and act within general policies across department levels Diversity and inclusion ASML is an Equal Opportunity Employer that values and respects the importance of a diverse and inclusive workforce. It is the policy of the company to recruit, hire, train and promote persons in all job titles without regard to race, color, religion, sex, age, national origin, veteran status, disability, sexual orientation, or gender identity. We recognize that diversity and inclusion is a driving force in the success of our company. Need to know more about applying for a job at ASML? Read our frequently asked questions.

1. 類比電路設計開發 2. 感測器元件開發與整合 3. 具CIS影像感測器相關類比IC電路設計驗驗者佳

[駐點於知名科技公司服務] 希望你對最新科技技術和EDA工具有強烈的學習熱情，並且願意參與從SYN、APR、signoff到Foundation IP最新技術的開發，將這些技術應用到最前沿的產品中。 1. 設計流程維護： 維護和優化CAD參考流程，助力IC設計。 確保設計流程性能和準確性達到最佳狀態，產出更優質的成果。 2. 工具整合： 整合各種EDA工具（如Synopsys、Cadence、Mentor Graphics）到參考設計流程中。 確保不同工具之間的相容性和無縫操作，提升工作效率。 3. 文件編寫: 創建和維護參考流程的全面文件。 詳細記錄所有更改和更新，方便用戶未來參考。 4. 性能監控： 監控參考流程的性能，識別改進區域。 實施增強措施，提高流程效率，縮短設計週期時間。

Responsible for developing custom IP for SoC design from specification definition, circuit design to testing, and familiar with component and process characteristics.

(1) DRAM電路設計與模擬驗證 (2) 具備DRAM ROW/COLUMN/CONTROL/DC/DLL任一或更多電路設計經驗者佳 (3) 具備verilog經驗者尤佳 (4) 了解基本UNIX操作，具備AWK等Programing能力者尤佳 (5) 具備電機電子資訊物理相關背景，無工作經驗可

1. Device characterization and test key design. 2. 元件量測並提供desinger相關規格數據 3. 記憶體陣列設計

The successful candidate shall possess the capability to design and analyze high speed, high performance analog / mixed signal circuits, including data converters, PLLs, and SERDES, in advanced CMOS FinFET technologies. She or he shall bring the design all the way to production. Imagine being part of a team that is fundamentally changing the way people communicate, the way they collaborate, the way they watch TV and explore the universe through the internet. Utilizing our uniquely differentiated technology, we have created an Intelligent Transport Network with more speed, capacity and scalability than ever before. Imagine a world with unlimited bandwidth. The network of tomorrow will allow for content and creativity limited only by the imaginations of its users. If this is something that interests you, that excites you, come take a look at a team not bound by large company obstacles and bureaucracy, where an idea today can be set in motion tomorrow. Come take a look at Infinera! Engaging in the high-speed analog circuit design, you have the chance to create the technical differentiation for Infinera to hold the market leadership. We together will revolutionize the era of efficient high speed transmission by building the cutting-edge circuitry. Your Key Responsibilities Would Include: Design, implement, and simulate the functionality and performance of various high-speed analog circuits, including the ADCs and DACs; Create the layout floor plans to optimize the overall performance; Supervise the layout activities and give concise guidelines to layout engineers, need to be hands on in drawing layout if necessary; Exploring the trade-offs of the different topologies and propose the best solution to achieve or exceed the requirements in terms of power/area/linearity/bandwidth, etc. Develop the analog testing plans and work with the PE/TE teams to characterize the functionality and performance of the products to ensure the quality; Need to support and comply with the team’s design methodologies and release flows. Mandatory Knowledge/Skills/Abilities: Must be extremely familiar with essential CAD tools, such as Cadence Virtuoso, Spectre, Incisive, Calibre, EMX, and Totem EM/IR, etc. Must have a proven tracking record of designing complex analog / mixed signal IPs or chips in deep submicron CMOS technologies. Must have experiences in bringing high performance analog IPs including but not limited to high-speed ADC, high-speed DAC, and high-frequency low-jitter PLL to production. Must have a decent understanding in CMOS analog / mixed signal design methodologies and circuit analysis; Must have a good understanding of device physics and the impacts of layout effects; Able to perform the behavioral modeling the blocks and circuits with Verilog-A or Verilog-AMS; Collaborative with other local or remote team members in a fast-paced professional environment. Preferred Knowledge/Skill/Abilities: Fluent in verbal and written communications; Independently resolves issues and conquer design challenges; Self-motivated and detail-oriented; Has the knowledge of (optical) communication theories and Matlab coding. Education and Experience Requirements: Minimum Requirement for Principal Design Engineer: M.S. in E.E. with 12+ years’ experience, or Ph.D. in E.E. with 8+ years’ experience

Hands-on experience in the design and development of at least one of the following analog circuits: ADC, DAC, PGA, high-speed analog driver, PLL, or SerDes.

1. 類比電路設計 2. 主要開發電源管理IC產品 3. DC-DC, Charger-Pump, LDO, PWM, OP相關電路設計 4. Layout 設計規劃

Digital IC design engineer - Familiar with Verilog RTL coding - Familiar with digital design flow (pre-layout simulation, timing constraint, synthesis, post-layout simulation) - Will be working on high speed Serdes IPs - Experience or interest in all-digital PLLs or clock-data recovery circuits is a big plus

Job description Join our innovative team specializing in cutting-edge embedded memory solutions. We are seeking Analog Circuit Engineers to play a key role in the design and development of high-performance embedded DRAM and associated peripheral circuits. In this position, you will be responsible for the complete cycle of DRAM circuit design and simulation verification. Your tasks will involve developing novel circuit topologies, transistor-level design, optimizing performance metrics, and ensuring robust functionality through extensive simulations using industry-standard EDA tools. Required qualifications include a strong technical background in Electrical Engineering, Electronics Engineering, Computer Engineering, Physics, or a closely related field. Candidates must possess demonstrated, significant experience in DRAM circuit design and comprehensive simulation verification methodologies. Ideally, candidates will have proven design experience in specific DRAM-related circuit blocks, including but not limited to: Row and Column Decoder circuits Control path logic DC-DC converters, Charge Pumps, and Bandgap References Delay Locked Loops (DLLs) and Phase Locked Loops (PLLs) Negative voltage generators (NVG) and other critical peripheral circuits This is an excellent opportunity to contribute to state-of-the-art embedded memory designs in a dynamic, collaborative environment. If you are a skilled analog designer passionate about solving complex challenges in DRAM circuitry, we encourage you to apply and help shape the future of embedded memory technology.

1.Work with team members and apply design techniques to work on different phases of complex logic design for ASIC/SOC project. 2. Working on the following tasks from time to time: HDL coding, documentation, RTL quality check, cooperate with back-end engineer etc.

1. 具備矽光子相關 EDA 版圖設計軟體 使用經驗（如 Cadence Virtuoso、Synopsys OptoDesigner、Luceda IPKISS 等）。 2. 熟悉矽光子 光學模擬與設計優化，能操作 Lumerical FDTD / MODE / INTERCONNECT 等模擬軟體，並具備量測與驗證能力。 3. 具備矽光子 / 光學測試 / 光學元件開發與設計相關經驗。 4. 具有良好的技術文件撰寫能力，能清楚表達設計思路與實驗結果。