「(CR20)類比IC設計工程師」的相似工作

1. Main responsibility is to design analog IPs in MCU such as adc/dac, pll, osc, por, ldo 2. 具備DC-DC Converter, Buck相關電路設計 2. Responsible for analog IP design, verification plan, test plan, document 3. Communicate with system, layout and digital engineer to ensure high quality --------------------------------------------------------------------------------------- 雅特力科技創立於2016年，為智原科技子公司。 【Artery雅特力】即將在台上市的IC設計公司，主要產品為32bit ARM core base MCU 公司網址：https://www.arterychip.com 關於雅特力：https://www.104.com.tw/company/1a2x6blojm

我們專注於能源晶片與深度演算法的融合創新，誠徵類比IC演算法工程師，將傳統的手工類比設計流程轉化為自動化的智慧演算法，讓電路設計更高效、更穩定，推動類比設計的未來。 你將負責： 開發電路拓撲分析演算法 設計 sizing 最佳化演算法（基於 gm/Id methodology 等） 將手工設計流程轉化為程式化流程 協助建立類比IC設計自動化工具 與軟體團隊合作進行演算法驗證與優化 熟練使用 Vibe Coding 工具（Cursor、Github Copilot、Claude… 等）更佳 我們期待你具備： 類比IC設計實務經驗 熟悉運算放大器、ADC/DAC、電源管理電路等拓撲設計 精通 SPICE 模擬與電路參數萃取 深度理解 sizing methodology（如 gm/Id 設計法） 能清楚闡述設計 trade-off 與電路原理 加分條件： 具備 Python 程式能力 有將手工設計方法轉換為程式實現的經驗 具備統計分析能力（Monte Carlo / corner analysis） 有 EDA 工具 API 開發經驗 熟悉圖論演算法與資料結構 如果你熱愛把設計方法變成程式，並用演算法重新定義類比IC設計的可能性，歡迎加入我們！

Digital IC design engineer - Familiar with Verilog RTL coding - Familiar with digital design flow (pre-layout simulation, timing constraint, synthesis, post-layout simulation) - Will be working on high speed Serdes IPs - Experience or interest in all-digital PLLs or clock-data recovery circuits is a big plus

Job description Join our innovative team specializing in cutting-edge embedded memory solutions. We are seeking Analog Circuit Engineers to play a key role in the design and development of high-performance embedded DRAM and associated peripheral circuits. In this position, you will be responsible for the complete cycle of DRAM circuit design and simulation verification. Your tasks will involve developing novel circuit topologies, transistor-level design, optimizing performance metrics, and ensuring robust functionality through extensive simulations using industry-standard EDA tools. Required qualifications include a strong technical background in Electrical Engineering, Electronics Engineering, Computer Engineering, Physics, or a closely related field. Candidates must possess demonstrated, significant experience in DRAM circuit design and comprehensive simulation verification methodologies. Ideally, candidates will have proven design experience in specific DRAM-related circuit blocks, including but not limited to: Row and Column Decoder circuits Control path logic DC-DC converters, Charge Pumps, and Bandgap References Delay Locked Loops (DLLs) and Phase Locked Loops (PLLs) Negative voltage generators (NVG) and other critical peripheral circuits This is an excellent opportunity to contribute to state-of-the-art embedded memory designs in a dynamic, collaborative environment. If you are a skilled analog designer passionate about solving complex challenges in DRAM circuitry, we encourage you to apply and help shape the future of embedded memory technology.

We are seeking a skilled Analog IC Design Engineer with expertise in MIPI TX/ PLL design and sensor readout circuits. The ideal candidate will possess a strong foundation in analog design and a passion for developing cutting-edge solutions in a collaborative environment. 1.Design and implement MIPI TX and PLL circuits for high-speed data transmission. 2.Develop charge pump and LDO (Low Dropout Regulator) circuits to ensure efficient power management. 3.Design and optimize oscillator (OSC) circuits for precise timing applications. 4.Create sensor readout circuits, including CDS (Correlated Double Sampling), TDC (Time-to-Digital Converter), ramp circuits, DAC (Digital-to-Analog Converter), and comparators. 5.Collaborate with system engineers to define specifications and ensure alignment with overall project requirements. 6.Perform circuit simulations and analyses using tools such as Cadence, Spectre, or HSPICE. 7.Conduct design verification and validation through prototyping and testing. 8.Optimize designs for performance, power efficiency, and reliability. 9.Participate in design reviews and contribute to project documentation. 10.Provide support during the layout and fabrication process. Preferred Qualifications: 1.Familiarity with IP design principles. 2.Experience with mixed-signal circuits. 3.Knowledge of low-noise and high-speed design techniques.

1. 顯示驅動IC 類比電路設計 2. 電源管理IC 類比電路設計 3. 高速介面 類比電路設計 4. 觸控類比前端感測類比電路設計

1. MSEE is required. 2. Solid background in analog integrated circuits. 3. Knowledge of high speed serial link technology. 4. Familiar with SerDes PHY (USB, PCIE Express, SATA and Thunderbolt) and building block (DFE, CTLE, CDR, PLL and FFE transmitter). 5. Experience in design and simulation high speed transceiver is a plus.

1. SAR ADC / Current steering DAC/ SDM ADC/ DAC related 2. Analog Baseband related 3. 據有類比整合相關經驗佳

1. 觸控IC、TDDI或指紋辨識 IC 開發經驗 2. ADC或sensor IP 開發經驗 3. TFT-LCD或OLED Display driver IC 開發經驗 4. Charge pump、LDO、Source driver、Gate driver、High speed interface、OSC、BGR 相關開發經驗 5. 工作地點：【台南、新竹、台北】 以上其中任何一項相關者佳。

1.LPDDR4/DDR4/DDR3 Mixed signal SERDES/PLL相關開發工作 2.Mixed signal SERDES RTL behavior analysis and implement,熟悉HSPICE 並具備 std cell design flow基礎佳

We are currently seeking a talented Analog Design Engineer to join our team and participate in the development of Power IC for High-Performance Computing (HPC). The role will primarily involve working on the design and development of the following components: 1. PMIC (Power Management Integrated Circuit) 2. Multiphase VR (Voltage Regulator) 3. Buck/Boost/Buck-Boost Converters 4. eFuse (Electronic Fuse)

Responsible for developing custom IP for SoC design from specification definition, circuit design to testing, and familiar with component and process characteristics.

1. NVM電路開發設計。 2. NVM週邊類比電路開發設計與佈局優化。 3. NVM電路整合開發設計。 4. 協助NVM測試晶片偵錯、驗證。 5. 協助客戶嵌入使用以及導入量產NVM IP產品。 研究所以上電子/電機相關系所畢，專長於類比電路設計、固態電子或功率半導體元件設計，有下線經驗者優先考慮。

【產品線描述】 1. LCD Power IC 2. 手機及穿載 Power IC 3. USB Type C Power delivery (MCU開發驗證經驗，相容性驗證) 【工作說明】 1. 面板及手機應用的電源管理, 背光驅動晶片開發 2. 需求條件: 2-1. 可獨立完成Buck, Boost, Buck-Boost 等DC/DC電路設計 2-2. 可獨立完成Charge Pump, LDO, OP等類比電路設計 2-3. 熟悉Battery Charger, Battery Protector尤佳 2-4. 熟悉ADC(Sigma-Delta, SAR), PLL尤佳 【共創A+聯詠】 穩健踏實、專家精神、創造優勢 驅動科技、開發創新、引領未來 邀請優秀人才，共創A+聯詠

Job desicription: Our Design Team specializes in the challenging field of Non-Volatile Memory (NVM) IC circuit design. We are actively seeking an experienced Analog Circuit Design Engineer to contribute to our cutting-edge developments in embedded NVM solutions and surrounding circuitry. As a key member of our team, you will be responsible for the design, verification, and debugging of essential analog building blocks like Bandgap references, LDOs, and Charge Pumps. A significant part of your role will involve designing critical memory peripheral circuits for NVM IP and test chips, including Array interfaces, Decoding logic, and Sense Amplifiers. Your responsibilities will span the design lifecycle, from contributing to IP specifications and core circuit design to ensuring performance through layout optimization and comprehensive corner simulations of NVM IPs. We are looking for candidates with proven expertise in analog circuit design, ideally with prior experience in embedded memory or NVM technologies. If you are an experienced analog designer eager to tackle complex challenges in non-volatile memory, we encourage you to apply and help shape the future of memory technology.

Analog IC design (A) Power Management(SMPS, Buck, Boost, LDO, Battery Charger)， (B) Analog Circuit Design

記憶體power system 設計 『具工作經驗者，薪資另議』

1. 16bit ADC/DAC design experience 2. PLL/DLL/RF/OSC/POR/LVDS design experience 3. LDO/DC-DC design experience 4.Guide layout engineer to make a compact & working layout

1.研究、設計、模擬與驗證類比及NVM IC電路。

- Responsible for entire analog design implementation that covers design specification, design creation, integration and optimization to layout review, final post-layout simulation, silicon characterization and system test and debug. - Experience in analog IP development that include SERDES, ADC, DAC, Audio Codec, PLL, IO, memory, analog blocks and high speed PHY for 130nm, 90nm and below technologies. - Knowledge in high speed PHY design (PCIE, USB, GbE, DDR, ETHERNET) is an added advantage. - Preferably done some test characterization, measurement and compliance in previous employment