「Analog Mixed-Signal Circuit Design Engineer_WLM (地點:新店or部分遠端)」的相似工作

Responsible for developing custom IP for SoC design from specification definition, circuit design to testing, and familiar with component and process characteristics.

Digital IC design engineer - Familiar with Verilog RTL coding - Familiar with digital design flow (pre-layout simulation, timing constraint, synthesis, post-layout simulation) - Will be working on high speed Serdes IPs - Experience or interest in all-digital PLLs or clock-data recovery circuits is a big plus

1. 顯示驅動IC 類比電路設計 2. 電源管理IC 類比電路設計 3. 高速介面 類比電路設計 4. 觸控類比前端感測類比電路設計

1. 類比IP相關功能的設計與實現 ADC, DAC, OSC, PLL, high speed interface...etc. 2. 類比IP設計方法和品質改進 3. 類比IP仿真與分析 4. 與第三方類比 IP 供應商合作 5. 與數位電路作co-sim

1. Main responsibility is to design analog IPs in MCU such as adc/dac, pll, osc, por, ldo 2. 具備DC-DC Converter, Buck相關電路設計 2. Responsible for analog IP design, verification plan, test plan, document 3. Communicate with system, layout and digital engineer to ensure high quality --------------------------------------------------------------------------------------- 雅特力科技創立於2016年，為智原科技子公司。 【Artery雅特力】即將在台上市的IC設計公司，主要產品為32bit ARM core base MCU 公司網址：https://www.arterychip.com 關於雅特力：https://www.104.com.tw/company/1a2x6blojm

1. SAR ADC / Current steering DAC/ SDM ADC/ DAC related 2. Analog Baseband related 3. 據有類比整合相關經驗佳

※實際任用職稱依個人相關經歷敘薪。 1. 熟悉Display Driver IC 原理. 2. 可獨立完成Charge Pump design. 3. 可獨立完成Band Gap, Regulators , LDO circuit design. 4. 熟悉類比電子電路專業知識如OP-AMP的設計 5 .個性主動積極、熱誠 、樂觀 . 6. 8~10年經驗 7. mipi. lvds frontend 設計與 debug 經驗尤佳

1. High speed ADC/DAC design(具備Ethernet PHY RX/TX 設計經驗佳) 2. ADC/DAC IP test 3. Familiar with behavior model simulation

【產品線描述】 高速傳輸 (USB4.0、DisplayPort、PCIe) 電路設計 (High Speed Serdes, Rx/Tx/Clocking, CTLE, DFE, CDR, PLL) 【工作說明】 高速介面、混合訊號類比電路設計 工作內容包含下列項目: 1. CDR architecture design (1/N-rate, DLL-based, PLL-based, PI-based)、DeMux 2. Adaptive CTLE/DFE 3. High speed ADC / Time-Interleaved ADC design 4. RF circuit related / EM related 5. PLL circuit/architecture design 6. High speed transmitter with FFE、P2S 7. High performance oscillator design (Ring/LC) 8. Impedance matching design 9. Circuit calibration techniques & flow 10. SerDes system behavior modeling & analysis 11. Chip Integration & Verification 【必要條件】 1. Master of Science / Above degree in Electrical Engineering, strong mixed-signal design concept. 2. 2-years above experience. 3. Familiar with design and simulation tools (Cadence's design environment, Circuit simulation : Spectre, HSpice, Finesim). 4. Strong debugging and analytical skills. 5. Clear communication skills and team work ability are necessary. 備註：上班地點為「台北」或「竹北」或「竹科」

- Responsible for entire analog design implementation that covers design specification, design creation, integration and optimization to layout review, final post-layout simulation, silicon characterization and system test and debug. - Experience in analog IP development that include SERDES, ADC, DAC, Audio Codec, PLL, IO, memory, analog blocks and high speed PHY for 130nm, 90nm and below technologies. - Knowledge in high speed PHY design (PCIE, USB, GbE, DDR, ETHERNET) is an added advantage. - Preferably done some test characterization, measurement and compliance in previous employment

Analog IC design (A) Power Management(SMPS, Buck, Boost, LDO, Battery Charger)， (B) Analog Circuit Design

1. Support customer projects from design-in, design-through to mass-production. 2. Team work with AE, FAE, RD and QA to solve problems.

Job description Join our innovative team specializing in cutting-edge embedded memory solutions. We are seeking Analog Circuit Engineers to play a key role in the design and development of high-performance embedded DRAM and associated peripheral circuits. In this position, you will be responsible for the complete cycle of DRAM circuit design and simulation verification. Your tasks will involve developing novel circuit topologies, transistor-level design, optimizing performance metrics, and ensuring robust functionality through extensive simulations using industry-standard EDA tools. Required qualifications include a strong technical background in Electrical Engineering, Electronics Engineering, Computer Engineering, Physics, or a closely related field. Candidates must possess demonstrated, significant experience in DRAM circuit design and comprehensive simulation verification methodologies. Ideally, candidates will have proven design experience in specific DRAM-related circuit blocks, including but not limited to: Row and Column Decoder circuits Control path logic DC-DC converters, Charge Pumps, and Bandgap References Delay Locked Loops (DLLs) and Phase Locked Loops (PLLs) Negative voltage generators (NVG) and other critical peripheral circuits This is an excellent opportunity to contribute to state-of-the-art embedded memory designs in a dynamic, collaborative environment. If you are a skilled analog designer passionate about solving complex challenges in DRAM circuitry, we encourage you to apply and help shape the future of embedded memory technology.

1. 類比IP相關功能的設計與實現 ADC, DAC, OSC, PLL, high speed interface...etc. 2. 類比IP設計方法和品質改進 3. 類比IP仿真與分析 4. 與第三方類比 IP 供應商合作 5. 與數位電路作co-sim

• 進行類比/混合訊號電路模擬(Spice, Spectre...) • 指導及協助Layout規劃佈局 • 撰寫設計、測試規格文件與書寫模擬報告 • 與測試工程師合作測試、驗證、Debug IC • Perform analog/mixed-signal circuit simulations (Spice, Spectre, etc.) • Provide guidance and assistance with layout planning • Write design and test specification documents and simulation reports • Collaborate with test engineers to test, verify, and debug ICs

1. 觸控IC、TDDI或指紋辨識 IC 開發經驗 2. ADC或sensor IP 開發經驗 3. TFT-LCD或OLED Display driver IC 開發經驗 4. Charge pump、LDO、Source driver、Gate driver、High speed interface、OSC、BGR 相關開發經驗 5. 工作地點：【台南、新竹、台北】 以上其中任何一項相關者佳。

1. 類比電路設計 2. 主要開發電源管理IC產品 3. DC-DC, Charger-Pump, LDO, PWM, OP相關電路設計 4. Layout 設計規劃

• 職稱：日班生產線領班 • 工作地點： Molex 新店廠（新北市新店區） • 主要工作內容： 　1. 負責每日工單執行：取號、配單、列印臨時條碼。 　2. 協助處理 CMES 系統不良判定與退換料流程。 　3. 執行首件確認及抽樣檢驗，確保產品品質穩定。 　4. 生產異常即時通報品管(QA)、工程(PE)及生產主管。 　5. 追蹤生產進度，依計畫調整人員與產能，確保交期。 　6. 熟悉文書作業，統計每日工時與產能數據，完成報表記錄。 7. 管理並協助作業員達到產能與品質目標。

1. 16bit ADC/DAC design experience 2. PLL/DLL/RF/OSC/POR/LVDS design experience 3. LDO/DC-DC design experience 4.Guide layout engineer to make a compact & working layout

1. 主動式電子掃描陣列 (相控陣列) 射頻元件及電路板佈局設計。 2. 評估與天線、熱控、電源、及機構之整合相容性，並進一步除錯和優化。