Responsible for developing custom IP for SoC design from specification definition, circuit design to testing, and familiar with component and process characteristics.
Digital IC design engineer
- Familiar with Verilog RTL coding
- Familiar with digital design flow (pre-layout simulation, timing constraint, synthesis, post-layout simulation)
- Will be working on high speed Serdes IPs
- Experience or interest in all-digital PLLs or clock-data recovery circuits is a big plus
1. 具 0~2年數位晶片設計,或有 0~5年類比晶片設計工作經驗。
2. 具備基本數位和類比電路知識,熟習標準晶片設計流程。
3. 熟習業界常用EDA tools, 或Matlab/ Simulink。
4. 研習過CMOS or BiCMOS 類比設計電路課程,對放大器有基礎認識。
5. Experience in these areas is preferred:
* BiCMOS or CMOS high-speed (>20Gb/s) circuit, Linear electrical amplifier &
equalizer, High-speed (>25G) CDR/PLL/SerDes.
* Linear optical laser driver & receiver (TIA + linear amplifier)
本職位負責類比IC電路的設計、驗證和除錯。這是一個高度技術性的職位,對公司的產品開發至關重要。我們正在尋找一位熱愛類比IC設計並具有相關經驗的人才,以推動公司的技術創新和發展。
如果您對這個職位感興趣,請投遞您的履歷表,我們立即與您聯繫。
1. Main responsibility is to design analog IPs in MCU such as adc/dac, pll, osc, por, ldo
2. 具備DC-DC Converter, Buck相關電路設計
2. Responsible for analog IP design, verification plan, test plan, document
3. Communicate with system, layout and digital engineer to ensure high quality
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雅特力科技創立於2016年,為智原科技子公司。
【Artery雅特力】即將在台上市的IC設計公司,主要產品為32bit ARM core base MCU
公司網址:https://www.arterychip.com
關於雅特力:https://www.104.com.tw/company/1a2x6blojm
• 進行類比/混合訊號電路模擬(Spice, Spectre...)
• 指導及協助Layout規劃佈局
• 撰寫設計、測試規格文件與書寫模擬報告
• 與測試工程師合作測試、驗證、Debug IC
• Perform analog/mixed-signal circuit simulations (Spice, Spectre, etc.)
• Provide guidance and assistance with layout planning
• Write design and test specification documents and simulation reports
• Collaborate with test engineers to test, verify, and debug ICs
Job description
Join our innovative team specializing in cutting-edge embedded memory solutions. We are seeking Analog Circuit Engineers to play a key role in the design and development of high-performance embedded DRAM and associated peripheral circuits.
In this position, you will be responsible for the complete cycle of DRAM circuit design and simulation verification. Your tasks will involve developing novel circuit topologies, transistor-level design, optimizing performance metrics, and ensuring robust functionality through extensive simulations using industry-standard EDA tools.
Required qualifications include a strong technical background in Electrical Engineering, Electronics Engineering, Computer Engineering, Physics, or a closely related field. Candidates must possess demonstrated, significant experience in DRAM circuit design and comprehensive simulation verification methodologies.
Ideally, candidates will have proven design experience in specific DRAM-related circuit blocks, including but not limited to:
Row and Column Decoder circuits
Control path logic
DC-DC converters, Charge Pumps, and Bandgap References
Delay Locked Loops (DLLs) and Phase Locked Loops (PLLs)
Negative voltage generators (NVG) and other critical peripheral circuits
This is an excellent opportunity to contribute to state-of-the-art embedded memory designs in a dynamic, collaborative environment. If you are a skilled analog designer passionate about solving complex challenges in DRAM circuitry, we encourage you to apply and help shape the future of embedded memory technology.
- Responsible for entire analog design implementation that covers design
specification, design creation, integration and optimization to layout review, final
post-layout simulation, silicon characterization and system test and debug.
- Experience in analog IP development that include SERDES, ADC, DAC, Audio
Codec, PLL, IO, memory, analog blocks and high speed PHY for 130nm, 90nm and
below technologies.
- Knowledge in high speed PHY design (PCIE, USB, GbE, DDR, ETHERNET) is an
added advantage.
- Preferably done some test characterization, measurement and compliance in
previous employment
1. 16bit ADC/DAC design experience
2. PLL/DLL/RF/OSC/POR/LVDS design experience
3. LDO/DC-DC design experience
4.Guide layout engineer to make a compact & working layout
1. MSEE is required.
2. Solid background in analog integrated circuits.
3. Knowledge of high speed serial link technology.
4. Familiar with SerDes PHY (USB, PCIE Express, SATA and Thunderbolt) and building block (DFE, CTLE, CDR, PLL and FFE transmitter).
5. Experience in design and simulation high speed transceiver is a plus.