「數位IC設計工程師」的相似工作

我們在尋找具備一定基礎的數位電路前端設計師加入我們的團隊。負責從 RTL 到 Netlist 的完整設計流程，並確保在設計符合市場需求規格的同時，達成高性能、低功耗及面積優化的需求。因此該職位需要了解 IC設計流程，以及業界主流 EDA 工具的實際應用經驗。 工作職責 - 根據設計規格撰寫 RTL - 根據驗證需求建構 verification environment - 執行功能驗證，確保設計的正確性和完整性 - 使用工具生成符合時序、功耗和面積要求的 netlist - 使用工具進行靜態時序分析，確保設計符合時序要求 - 配合前後端工程師，協助完成佈局與布線流程，並確認產出之電路在時序、功耗等方便符合規格 - 分析並解決設計中的時序、功耗及訊號完整性問題

1. IC產品之研發與應用設計 2. 建立IC產品基礎規格並設計IC電路 3. 降低產品成本，提高IC品質，支援軟/硬體開發 4. 熟數位IC設計及相關工具 Verilog HDL、Cadence IES simulator 、FPGA tools、Synopsys DC

1. 有TDDI IC開發經驗, AFE/DSP/MCU 開發經驗者 2. 有IC串接與MCU協同架構開發經驗者 3. 有開發TFT-LCD面板相關時序控制器經驗者 4. 有數位訊號經驗與通訊原理者尤嘉

1. 參與公司數位後段設計 之產品開發 2. 熟悉與維護 並參與 新流程之開發

This is a good opportunity to join a startup company working in UWB and Radar product. Co-work with ASIC design team for product development competive salary and startup package 工作內容: - 協助 Radar 定位演算法DSP實現及其驗證 - 協助數位晶片Serial介面(I2C/SPI)開發 - 協助產品驅動程式開發和相關測試 具備條件: - 具3年以上Digital IC design或FPGA開發相關經驗 - 熟悉RTL coding、simulation & synthesis流程及其開發工具使用 - 具C/C++ coding 和 debug 能力 - 能理解基礎數位運算原理如FIR IIR cordic佳

我們專注於3D影像立體雙目視覺技術 產品應用於3D 影像辨識、360 度環景拍照、攝影或AR 與VR 職務內容： ★ USB2.0/3.1或 MIPI 介面之2D/ 3D 影像處理與壓縮之 IC 開發 ★ 影像處理與壓縮相關數位 IP暨產品之開發設計、測試、驗證 條件要求： 1. 對IP Verification, System Verification 有興趣 2. 熟Verilog coding 與 ASIC design Flow 與 Timing Closure 3. 或有 SoC IC 開發經驗 4. 對開發人工智慧((AI) 晶片與邊緣運算有興趣者

1. IDC觸控數位電路設計 (AFE) 2. SOC周邊數位電路設計 3. SOC數位電路整合

【工作內容】 • Work with team members and apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market • Provide the technical leadership to the DV team for the project • Work independently on various DV tasks and provide technical guidance to the DV team. • Be involved technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup 【職務條件】 • Master’s degree in Electrical Engineering, Computer Science, or related. • Good understanding of ASIC design verification flow. • RTL coding with Verilog/System Verilog and familiar with front-end design flow and C/C++ programming experiences. • Knowledge of Perl, OVL, SVA, SV, UVM, OVM, script programming, etc. 【其他條件】 • MSEE with a minimum of 5 years, or BSEE with a minimum of 8 years of experience in digital ASIC/SOC design verification • MS/BS degree in EE or CS with expertise in digital IP/SOC design verification.

Responsible for digital IP coding and micro-architecture design of low-power, high-performance LLM inference accelerators. Drive mapping of lightweight frameworks such as llama.cpp onto NPU, plan compute/memory subsystems, and optimize quantization & KV-cache for production-ready LLM SoCs. Write RTL specs and guide DV plans and P&R convergence for PPA targets. 1. 研讀規格。 2. IC數位邏輯線線路的研發設計。 3. IC數位邏輯線路模擬與合成。 4. FPGA的合成規劃與測試驗證。 5. IC的靜態時序分析 (Static Timing Analysis)。 6. IC佈局後的線路模擬。 7. 撰寫IC規格設計書。 8. IC的除錯與工程變更修改。 9. 協助系統應用部門的進行IC驗證版的規劃。

1. SOC/IP 整合工作，從RTL到 Netlist 2. clock tree structure design 3. Lint / CDC check / Synthesis/ DFT/ LEC

- 用Verilog/SystemVerilog撰寫RTL，負責數位電路介面與模擬驗證。 - 參與晶片模組整合與ASIC合成（含DFT、時序收斂）到Tape-out。 - 主導設計專案與SoC整合。 - 帶領小團隊（3人），負責任務分配與技術指導。

負責IP開發、整合與偵錯 -- 利用Verilog/SystemC從事邏輯設計與數位系統設計，以相關自動化軟體進行電路合成及模擬驗證，並配合利用FPGA系統平台進行系統整合與測試驗證。

數位IC設計

1. SerDes CTRL IP RTL 開發與維護 (例如LPDDR､UFS､NAND Controller...) 2. 設計驗證 3. FPGA相關設計與實作 以上工作依個人意願酌情分配

1.數位IP相關功能的設計與實現 2.數位IP仿真與FPGA驗證 3.數位IP/subsys/chip_top的前段整合流程signoff 4.ISO 26262 FMEDA 設計和品質改進 5.與第三方數位 IP 供應商合作

1. 負責數位類比整合，協助晶片bring-up，除錯與特性分析。 2. 建立FPGA 。 3. Check Layout Plan。 4. 團隊合作達成晶片面積目標 。 5. 合作驗證，並建議測試計畫與驗證的方法 。 6. 根據規格，整合公司內部與外部IP 。 7. 與系統部門合作，了解系統與電路結構與系統需求 。

Job Description: Microchip’s Wireless Solutions Group is seeking a FPGA engineer to support SOC development for our next generation, mixed signal, wireless products. The role will focus on the areas of RTL design, FPGA synthesis and FPGA system bring-up, debug and validation. It will require a proactive candidate with a proven record of success in cross functional and cross site team environments. Key Responsibilities: • Collaborate with the design team to develop and optimize the RTL for FPGA , ensuring its efficiency and functionality. • Conduct FPGA synthesis using industry-standard tools to transform RTL code into a target FPGA device. • Assist in the initial bring-up of the FPGA system, ensuring proper functionality and identifying and resolving any issues that may arise. • Perform through testing and validation of the SOC design, both at the RTL level and in the FPGA implementation, and resolve any bugs or issues that are discovered. • Collaborate closely with the FW (Firmware), Validation, and RF teams to successfully carry out FPGA system bring-up, debug, and validation activities.

1.影像高速IP開發驗證相關工作 2.RTL coding/synthesis/simulation/verification

As senior/staff digital design engineer, this person is required to support all digital design activities on company products, design services as well as internal IP development. Below are the responsibilities: - Responsible for RTL Design and writing of test bench - experience in IP core design such as peripheral interfaces, CPU cores, digital controllers - Architecture review, RTL design, functional verification, post synthesis simulations. - Responsible for SOC system Integration & verification - Experience in SoC Architecture and Microarchitecture A - Experience in ARM CPU integration to SoC - Experience in SDRAM Memory Controller integration - Experience in interconnect matrix, AHB Bus Arbitration, multi-layer AHB Bus architecture - Experience in SoC Peripherals design: GPIO, RTC, UART, I2C, I2S, and SPI - Excellent in Verilog RTL coding and simulation - Familiar with FPGA prototype and verification - SD/SDIO relative experience is an added advantage. - AMBA Interface relative experience is an added advantage. - Knowledge in controller design (USB, PCIe, SATA, and Ethernet) is an added advantage. - Preferably done some FPGA prototyping in previous employment Desired Skills & Competency Requirement: - Verilog RTL coding - SoC design flow and SoC peripheral IP design - FPGA prototyping and emulation - System validation and verification - Characterization and the handling of test equipment - Digital front-end design, simulation and synthesis - Verification in system Verilog OVM - Low power synthesis methodology - Digital support on DFT and ATPG - Scripting in Perl, Python, TCL, UNIX, Linux

【產品線描述】 Evolution Video Display 新興顯示器開發： 1. Gaming monitor controller for LCD, OLED and Mini-LED. 專業電競螢幕，極致沉浸競界曲面螢幕，遊戲體驗身歷其境 2. Public display controller for LCD and Micro/Mini-LED. 大型商用顯示器，極窄邊框拼接電視牆，電子白板 3. Electronic Vehicle Display Controller. AR/2D HUD(抬頭顯示器)，車用高速顯示介面 4. Advanced Projector Controller. 低延遲的遊戲投影機、短焦投影機、浮空影像顯示器 【工作說明】 電路硬體設計與開發 1. 顯示器或車用顯示系統架構開發 (System Architecture Development) (a) CPU/MCU架構整合 (b) SoC system bus 與 bridge架構規劃設計 Familiar with AXI/AHB/APB/Arbiter (c) DDR memory controller 2. 高速數位介面 High-Speed I/F (a) HDMI TX/RX link layer (HDMI1.4/2.0/2.1) (b) DP TX/RX link layer (DP1.4/2.0) (c) MIPI RX link layer (d) Vx1 link layer (e) USB Type-C controller 3. Picture Quality(PQ) (a) 視訊影像處理,色彩轉換演算法開發有興趣或具經驗 (b) HDR10+, Dobly Vision 4. FPGA 平台設計 5. APR flow (a) Synthesis/STA (b) DFT (c) Low-power flow (d) APR co-work 【必要條件】(熟悉或有相關經驗) 1. 顯示器或車用顯示 CPU/MCU/DDR controller/bus bridge相關經驗 2. 高速數位介面 High-Speed I/F HDMI TX/RX / DP TX/RX / Vx1 相關經驗 3. Picture Quality(PQ) 視訊影像處理經驗 車用相關IC 設計經驗 4. SOC 整合經驗