「S－ ADV 設計驗證工程師｜知名微處理器&IC設計大廠專案（台北/新竹）」的相似工作

We are seeking a highly motivated Design Verification Engineer to join our dynamic team. You will be responsible for ensuring the functional correctness of complex digital designs using industry-leading verification methodologies such as UVM, Formal Verification, and Coverage-Driven Verification. 【Key Responsibilities】 · Develop detailed verification plans based on design specifications and architectural documents. · Build and maintain System Verilog UVM-based testbenches for SoC/Subsystem/IP-level verification. · Write constrained-random and directed test cases to validate functionality, performance, and corner-case scenarios. · Perform coverage analysis (functional coverage, code coverage, assertions coverage) and drive towards coverage closure. · Apply Formal Verification techniques (e.g., property checking, connectivity checking) where applicable. · Support simulation regression runs and maintain automation scripts (Perl/Python/TCL/Makefile). · Participate in design and verification reviews, providing valuable feedback to improve quality.

我們專注於3D影像立體雙目視覺技術 產品應用於3D 影像辨識、360 度環景拍照、攝影或AR 與VR 職務內容： ★ USB2.0/3.1或 MIPI 介面之2D/ 3D 影像處理與壓縮之 IC 開發 ★ 影像處理與壓縮相關數位 IP暨產品之開發設計、測試、驗證 條件要求： 1. 對IP Verification, System Verification 有興趣 2. 熟Verilog coding 與 ASIC design Flow 與 Timing Closure 3. 或有 SoC IC 開發經驗 4. 對開發人工智慧((AI) 晶片與邊緣運算有興趣者

Responsibilities: • Develop integrated verification environment. • Verify designs with system verilog and system verilog assertion. • Build, maintain and upgrade testbenches and their components using UVM-based methods. • Check functional coverage and code coverage • Create controlled random testcases. Pre-debug and provide debug reports. • Scripting experience using scripting languages like Perl and Python.

Job Description: In this position the individual will develop test environment, test plan, and test cases based on the product specification and related industrial standards. The individual will require initiating a test plan review with the team and updating the test plan accordingly. The candidate will require executing and developing the test cases based on test plan, debugging and reporting the test result to achieve full function coverage goal. The individual will require developing ASIC bench functional test programs and doing ASIC bring-up and ASIC bench testing. The ideal individual must have proven ability to achieve results in a fast moving, dynamic environment. The candidate must have ability to coordinate priorities and initiatives and clear communication skill.

(a) 負責Tcon IC開發 (b) 負責數位影像處理IP開發 (C) 1.整合使用 FPGA IP，具模擬驗證以達功能的需求 2.系統驗證項目的規劃及系統整合與測試 3.開發、撰寫及驗證 Verilog code (D) 1.使用System Verilog、UVM驗證數位IP 2.依據規格擬定測試計畫並建立隨機測試向量 3.與Design Team密切合作，提高function/code test coverage

使用最新的IC驗證方法對晶心的CPU設計做高強度測試，以提升CPU設計的品質與完整度。此職務可以累積對計算機架構，微架構，與嵌入式系統的廣泛知識。具體內容包含: * Understanding uarch of Andes processor designs * Creating verification plans * Implementing test environments * Generating test cases * Improving test coverage * Identifying CPU bugs in various environments (simulation, FPGA, etc.) * Test automation * Performance benchmarking

1. Design verification with SystemVerilog/UVM, C/C++ 2. Integration test environment with VIP 3. Develop checker and scoreboard. 4. Verify design with SystemVerilog assertion. 5. Test plan for a verification task. [Requirement] 1. Familiar with SystemVerilog HDL, OOP, Python, TCL, and shell programming. 2. Better to have SoC design and bus concept.

⚠️特別說明：此職位需on-site在新竹清大創新育成中心辦公室，無提供遠端工作條件。 ✅主要職責： 1. 高效能記憶體子系統（DDR/LPDDR Subsystem）之整合、開發與驗證。 2. 參與GenAI SoC設計，包括架構規劃、RTL設計、模擬與驗證。 3. 配合後端設計團隊，進行時序分析與設計優化。 5. 進行設計文件撰寫與維護，確保設計過程符合公司開發流程。 6. 針對客戶需求，進行系統分析與客製化設計開發。 ✅基本要求： 1. 電機、電子、資訊工程相關科系畢業，學士以上學歷。 2. 具備5年以上數位IC設計經驗。 3. 熟悉 DDR PHY 架構、控制器、timing calibration與 training 流程 4. 熟悉SoC Bus Fabric設計，具備AXI、AHB等匯流排介面經驗。 5. 熟悉RTL設計 (Verilog / System Verilog)。 6. 了解前端設計流程，包括模擬、合成、時序分析等。 7. 良好的問題分析能力，具備團隊合作精神。 ✅加分條件： 1. 有參與過 LPDDR Subsystem Integration與Silicon Tape-out 並成功量產 2. 熟悉 Synopsys LPDDR、Cadence GDDR IP/Subsystem 3. 熟悉 UPF、低功耗設計流程 4. 熟悉 DFT 、Scan、BIST ✅ Why Join Us 1. 與頂尖技術團隊共事，參與高效能 AI/高速記憶體解決方案開發 2. 自主創新文化，提供技術發揮與產品影響力兼具的工作環境

ASIC design engineer responsible for post-RTL design flow. He/She will be responsible for block and /or chip level synthesis, timing closure, DFT generation, and ECOs. The responsibilities include but are not limited to. •    Improve the design methodology and flow. •    Synthesis, timing closure, and DFT support for various types of SerDes IPs ranging from 10Gbps to 224Gbps data rates for different applications. •    Collaborate with Analog/Digital design teams to deliver competitive SerDes IP solutions for all the Marvell product lines. •    Provide support to the product teams, for both pre and post-silicon

1. IC產品之研發與應用設計 2. 建立IC產品基礎規格並設計IC電路 3. 降低產品成本，提高IC品質，支援軟/硬體開發 4. 熟數位IC設計及相關工具 Verilog HDL、Cadence IES simulator 、FPGA tools、Synopsys DC

1. 支援計畫功能與系統驗證與除錯。 2. 規劃及協調驗證資源、項目及時程。 3. 與Hardware engineer 溝通設計FPGA硬體架構規劃 4. 與Software engineer 溝通設計FPGA 控制介面 5. SoC FPGA系統整合。 6. 演算法之RTL實現或IP整合、獨立撰寫 Testbench & Debug FPGA電路 7.高速介面(HDMI/eDP/3G-SDI/12G-SDI)、DDR、I2C、UART、SPI等介面整合應用 8. 具醫療影像及色彩處理開發

【工作內容】 • 我們正在尋找具備先進製程經驗的 IC Layout 工程師，加入團隊後可以參與高階SoC /Analog IP 的實體實現，並負責以下工作： -Mixed-Mode FinFET Layout 設計與繪製，確保電路佈局在效能、面積與可靠性之間取得最佳平衡。 -進行 FinFET 製程相關的 DRC / LVS / ERC 驗證，確保設計符合法規與 Foundry 要求。 -熟悉 XRC & EM/IR 分析流程，進行可靠性評估，並針對潛在問題提出改善方案。 【職務條件】 • 必備條件：具備 FinFET 製程經驗，能獨立進行版圖設計與驗證。 -具備類比電路佈局經驗，了解電路特性與佈局考量，能與設計工程師密切合作。 -具備良好的溝通能力與團隊合作精神，能在專案時程內交付高品質成果。

- 用Verilog/SystemVerilog撰寫RTL，負責數位電路介面與模擬驗證。 - 參與晶片模組整合與ASIC合成（含DFT、時序收斂）到Tape-out。 - 主導設計專案與SoC整合。 - 帶領小團隊（3人），負責任務分配與技術指導。

Familiar with digital IC design verification flow is a plus. Familiar with SV/UVM is a plus. Familiar with PCIE/NVMe is a plus. You will be in charge of making testplan according to the specification. You will take participate in creating verification testbench, test writing/debugging, and regression convergence. We focus on the storage related IP and prospective features. We provide high flexibility with days off and competitive salary.

Job Description We are seeking a highly skilled ASIC Verification Engineer to join our team in Chupei, Taiwan. In this role, you will be responsible for developing and implementing comprehensive verification strategies for complex ASIC designs, ensuring the highest quality and reliability of our semiconductor products. Develop and execute verification plans for complex ASIC designs Create and maintain testbenches using SystemVerilog and UVM Design and implement efficient verification environments Perform functional and formal verification of digital designs Develop automated test scripts to improve verification efficiency Analyze and debug design issues identified during verification Collaborate with design engineers to resolve functional discrepancies Generate detailed verification reports and documentation Stay updated with industry trends and emerging verification methodologies Contribute to the continuous improvement of verification processes and tools Qualifications Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field 5+ years of experience in ASIC verification with strong proficiency in SystemVerilog and UVM Experience with Verilog, VHDL, and industry-standard simulation tools (e.g., Synopsys VCS, Cadence Xcelium) Experience of CPU, GPU, NPU or HBM verification Knowledge of formal verification techniques and tools Strong debugging, problem-solving, and analytical skills Solid understanding of digital logic design, computer architecture, and communication protocols Excellent organizational skills with strong attention to detail Good communication and teamwork skills in a fast-paced environment

請務必投遞官網(12475): https://careers.synopsys.com/job/hsinchu/applications-engineering-sr-staff-engineer/44408/85440860528 You Are: You are an innovative and resourceful engineer with a deep curiosity for solving complex technical challenges at the intersection of hardware and software. With a strong foundation in Electronic Engineering, Computer Science, or a related field, you are adept at leveraging your programming expertise—whether in Python, Tcl, Perl, or similar languages—to streamline and enhance engineering workflows. Your experience within UNIX/Linux environments equips you to navigate high-performance computing scenarios with ease. You thrive in collaborative, cross-functional teams and are energized by the opportunity to work closely with top-tier foundry partners and leading fabless companies. Your keen understanding of physical verification flows—such as DRC, LVS, PERC, FILL, and DFM—sets you apart, and you are eager to deepen your expertise in SoC physical design enablement, process effect analysis, and signoff. You are detail-oriented, capable of producing clear technical documentation, and communicate with clarity and empathy across diverse audiences. What You’ll Be Doing: 1.Delivering advanced physical verification solutions (DRC/LVS/PERC/Fill) for top-tier foundries and key fabless customers, ensuring high-quality silicon signoff. 2.Developing and validating process design kits (PDKs) and verification methodologies in collaboration with R&D and customer teams. 3.Partnering with R&D to innovate and improve Synopsys tools and flows, contributing to the evolution of physical verification technologies. 4.Providing hands-on customer support, troubleshooting issues, and delivering timely resolutions that enhance customer satisfaction and product adoption. 5.Coordinating with internal teams, including product managers and end-users, to align on best practices and ensure seamless integration of new technologies. 6.Documenting technical solutions, validation methods, and customer workflows for knowledge sharing and process improvement. 7.Staying up to date on industry trends and applying new insights to continuously optimize verification processes and tools. The Impact You Will Have: Accelerate the adoption and success of Synopsys physical verification products in leading-edge semiconductor manufacturing processes. Drive the development of robust PDKs and methodologies that enable customers to achieve first-time-right silicon. Enhance the quality and reliability of Synopsys verification tools through direct feedback and collaborative innovation with R&D teams. Strengthen Synopsys’ reputation as a trusted partner to top-tier foundries and fabless customers worldwide. Facilitate faster product cycles and reduced time-to-market for customers by delivering efficient and effective signoff solutions. What You’ll Need: BS or MS degree in Electronic Engineering, Computer Science, or a related field. Proficiency in at least one programming language, such as Python, Tcl, or Perl. Hands-on experience with UNIX/Linux environments and command-line tools. Familiarity with physical verification flows (DRC, LVS, PERC, FILL, DFM) and understanding of complex layout/electrical design rules. Strong investigative, analytical, and problem-solving abilities, with a passion for learning new technologies. Ability to produce clear, concise technical documentation and validation reports. Prior knowledge of tool/runset development/support and experience with SoC physical design is a plus.

1. Architecture design and RTL implementation of Automotive/Smartphone chipset 2. SoC system power and performance analysis 3. SoC system bus and memory subsystem design, integration, and modeling 4. SoC low power design, integration, and modeling 5. SoC functional safety analysis, design, integration, and modeling 6. SoC cyber security analysis, design, integration, and modeling

【職務內容】 1.負責 USB host Windows Driver (U2/U3/U4) 與 ARM 架構相關開發與維護。 2.協助處理 OEM 回報問題 (IoT / Stability / USB-IF)。 3.修改 USB host code 以進行 Debug 與問題解決。 4.與 Microsoft 與 GPU 廠商合作，分析並解決系統相容性問題。 5.參與 Preloader、UEFI、TF-A、Windows (ARM) 系統開發。 【職務需求 】 1.精通 C 語言，熟悉 Windows / ARM 平台。 2.熟悉 GitHub 協作流程。 3.具備 USB/PCIe protocol 系統 Debug 經驗。 4.熟悉 PD / Retimer / EC 相關知識。 5.具備硬體基礎概念，能閱讀 PCB 電路圖，能操作 示波器、分析儀。 6.具 Microsoft 合作經驗者佳。

1.Integrated verification environment 2.Familiar with SoC level and IP level verification methodology 3.Develop verification plan and optimize verification flow 4.Familiar with verification methodology such as UVM, VMM, or OVM 5.Team player

針對數位 IC / SoC / IP 設計進行驗證規劃與測試流程設計。 撰寫驗證計畫 (Testplan)、測試規格與測試案例。 建立與維護 UVM / SystemVerilog 等驗證環境與 testbench。 撰寫 constrained-random / directed testcases，並進行功能覆蓋率 (functional coverage) 與程式碼覆蓋率 (code coverage) 分析。 協助 debug，與設計工程師 (RTL designer) 一同定位與修正問題。 導入並應用 EDA 驗證工具 與跨部門團隊合作，確保設計符合規格與品質。 給新鮮人的你 工作內容: 我們的驗證工程師主要負責確保晶片設計「照著規格跑得正確」。 如果你剛畢業或經驗不多也不用擔心，我們有完整的培訓和資深同事手把手帶領！ 你會接觸到： 學習並建立 晶片驗證環境 (使用 SystemVerilog / UVM)。 撰寫測試案例，模擬晶片設計的各種情境。 分析模擬結果，協助 debug，和設計工程師一起找出問題。 了解 EDA 工具的使用 (simulation、lint、formal 等)。 與團隊合作，確保設計符合規格。 我們希望你具備 (Requirements) 電機、電子、資訊工程或相關科系學士/碩士畢業。 具備 數位電路基礎。 會一點點程式語言 (C/C++、Python、Verilog、SystemVerilog 任一皆可)。 對半導體產業與晶片設計有熱情，願意學習新技術。 樂於團隊合作，遇到問題願意溝通與討論。