「數位驗證工程師Digital Verification Engineer」的相似工作

a. Job Description: We are looking for a highly motivated RTL Designer to join our team in developing high-performance digital IPs. The ideal candidate will have experience in Register Transfer Level (RTL) design and verification, with a strong understanding of digital logic, microarchitecture, and ASIC/FPGA development processes. The role involves designing and verifying custom hardware IPs for cutting-edge applications. b. Verification: Develop and execute test plans to verify functionality, performance, and power requirements. Create testbenches using SystemVerilog/UVM for functional verification. Perform simulation, debugging, and root cause analysis for design issues. Conduct code coverage and functional coverage analysis to ensure comprehensive testing. Collaborate with verification and firmware teams to validate IP functionality. c. Qualifications: Bachelor’s/Master’s degree in Electrical Engineering, Computer Engineering, or a related field. 2+ years of experience in RTL design and verification. Proficiency in Verilog, SystemVerilog Strong understanding of digital design concepts, including pipelining, clock domains, and low-power design techniques. Experience with simulation tools (e.g., ModelSim, VCS, Questa) and formal verification techniques. Familiarity with UVM methodology and testbench development. Knowledge of scripting (Python, TCL, Perl, Shell) for automation. Experience with FPGA or ASIC development flows, including synthesis and timing analysis. Strong debugging and problem-solving skills. Excellent communication and teamwork abilities. - Non smoking

Job Description The successful candidate shall possess abundant experience in designing complex DSP for communication systems. She/he shall also have decent knowledge in analog/mixed-signal circuitry to perform the modeling and optimization of the overall high-performance front ends for communication SoCs. Imagine being part of a team that is fundamentally changing the way people communicate, the way they collaborate, the way they watch TV and explore the universe through the internet. Utilizing our uniquely differentiated technology, we have created an Intelligent Transport Network with more speed, capacity and scalability than ever before. Imagine a world with unlimited bandwidth. The network of tomorrow will allow for content and creativity limited only by the imaginations of its users. If this is something that interests you, that excites you, come take a look at a team not bound by large company obstacles and bureaucracy, where an idea today can be set in motion tomorrow. Come take a look at Infinera! Engaging in the design and implementation of the high-speed, highperformance analog / mixed-signal verifications, you have the chance to create the technical differentiation for Infinera to hold the market leadership. We together will revolutionize the era of efficient high-speed transmission. Essential Functions and Key Responsibilities: • Model the circuit blocks and mixed-signal IPs, including but not limited to high-speed ADCs, DACs, CTLE, FFE, and PLLs, to work with the architect and designers to achieve the optimal system-level performance. • Perform the functional verification and timing analysis on the IPs and the blocks. • Work with the digital verification team to generate the adequate interface to ensure the timing and connectivity. • Performs co-simulations on analog blocks and digital blocks in the mixed-signal simulation environment. Mandatory Knowledge/Skills/Abilities: • Has intimate knowledge of UVM verification flow. • Have prominent tracking record in modeling and verification of analog/mixed-signal IPs, including but limited to SERDES, optical links, and wireless transmission systems. • Hands-on in modeling and simulating with System-Verilog (WREAL), Verilog-AMS, and/or C, C++. • Have a decent understanding in CMOS analog / mixed signal design. Preferred Knowledge/Skill/Abilities: • Able to create IBIS-AMI model. • Can code in System-Verilog (WREAL). • Fluent in verbal and written communications. • Independently resolves issues and conquer design challenges. • Self-motivated and detail oriented. • Has good interpersonal skills. Education and Experience Requirements: • M.S. in E.E. with 8+ years’ experience, or Ph.D. in E.E. with 6+ years’ experience Additional Job Description: Infinera is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, religion, color, national origin, sex, age, status as a protected veteran, or status as a qualified individual with disability.

【工作內容】 • Work with team members and apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market • Provide the technical leadership to the DV team for the project • Work independently on various DV tasks and provide technical guidance to the DV team. • Be involved technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup 【職務條件】 • Master’s degree in Electrical Engineering, Computer Science, or related. • Good understanding of ASIC design verification flow. • RTL coding with Verilog/System Verilog and familiar with front-end design flow and C/C++ programming experiences. • Knowledge of Perl, OVL, SVA, SV, UVM, OVM, script programming, etc. 【其他條件】 • MSEE with a minimum of 5 years, or BSEE with a minimum of 8 years of experience in digital ASIC/SOC design verification • MS/BS degree in EE or CS with expertise in digital IP/SOC design verification.

*大學月薪33800元 / 碩士月薪38600元 1.申請與執行研究計畫。 2.負責報帳、經費申請、物品建檔等行政工作。 3.操作並維護計劃或實驗相關的設備與儀器。 4.協助資料收集和資料分析。 5.編輯、撰寫計畫報告書。

We are looking for talented engineers to join our VLSI Verification team. You’ll work on next-generation SoCs, applying advanced verification methodologies (SystemVerilog/UVM, coverage-driven, assertion-based) and leveraging AI-assisted tools to accelerate testplan writing, assertion development, and debug. Responsibilities • Develop and execute verification plans for complex SoCs/IPs • Build testbenches, assertions, and coverage models • Collaborate with architects, designers, and post-silicon teams • Ensure correctness and reliability of cutting-edge designs Why Join Us • Cutting-edge verification with AI-powered flows • Work alongside global world-class engineers • Accelerated growth in a learning-driven culture If you are smart, curious, and eager to learn, join us and shape the future of silicon innovation! 我們正在尋找聰明好學的工程師，加入我們的 VLSI Verification 團隊。 這裡沒有高壓的文化，而是重視 自主、學習與創新。我們相信工程師應該能專注在真正有價值的問題上，並透過 simulation 與 formal verification 技術搭配 AI 輔助，大幅提升驗證效率。 工作內容 • 開發與執行 SoC/IP 驗證計畫 • 使用 simulation (模擬) 與 formal (形式驗證) 技術，確保設計正確性與可靠性 • 建立 testbench、assertion、coverage model • 與架構師、設計師及 post-silicon 團隊合作完成驗證流程 • 善用 AI 工具 加速 testplan 撰寫、assertion 開發與 debug 我們能提供 • 外商文化：自主彈性、無高壓管理，重視結果與學習 • 技術前沿：結合 simulation + formal verification 與 AI 驅動流程 • 成長環境：與世界級跨國工程師共事，快速提升專業實力 • 全球影響力：你的成果將應用於數百萬使用者的產品 如果你聰明、積極、樂於學習，想在自由又專業的環境中挑戰自我， 歡迎加入我們，和我們一起打造下一代晶片驗證技術！

1.針對數位電路IP Spec撰寫testcase 與相容性測試 2.有SOC與FPGA前端驗證經驗 3.熟悉數位IC設計流程和相關EDA工具 4.有大型複雜電路或serdes CTRL驗證經驗者尤佳

1. Design verification with SystemVerilog/UVM, C/C++ 2. Integration test environment with VIP 3. Develop checker and scoreboard. 4. Verify design with SystemVerilog assertion. 5. Test plan for a verification task. [Requirement] 1. Familiar with SystemVerilog HDL, OOP, Python, TCL, and shell programming. 2. Better to have SoC design and bus concept.

1. Responsible for SOC physical implementation including floorplan, power plan, physical synthesis, clock tree, routing, RC, STA, timing closure, EM/IR, DRC/LVS to GDS out. 2. Responsible for APR physical design flow development & automation

(a) 負責Tcon IC開發 (b) 負責數位影像處理IP開發 (C) 1.整合使用 FPGA IP，具模擬驗證以達功能的需求 2.系統驗證項目的規劃及系統整合與測試 3.開發、撰寫及驗證 Verilog code (D) 1.使用System Verilog、UVM驗證數位IP 2.依據規格擬定測試計畫並建立隨機測試向量 3.與Design Team密切合作，提高function/code test coverage

- 類比sensor 驗證與除錯與產生驗證報告 - IC datasheet 與技術文件撰寫 - EVB and Test board 設計 - 建立系統模型 - 客戶產品應用支援

## 職務說明 - 應用於無人機雷達系統 - 數位IP架構設計與實作。 - 透過MATLAB/C++協助數位IP驗證 - 透過FPGA整合與驗證。 ## 技能要求 - 具備數位訊號處理經驗 - 具備數位電路設計經驗 - 程式語言必要：Verilog/VHDL, TCL, ##加分條件： - 具備雷達/通訊訊號處理、數位設計架構 - 具備RF/Analog 知識與RF/Analog校準設計 - 程式語言: MATLAB, python, c, c++, Chisel3

由於先進製程與高整合度晶片需要較長的研發時間及高製造成本，DV (Design Verification) 已成為聯發科技晶片開發流程中不可或缺的一環。 CDG DV部門負責開發與執行最高整合度 Smartphone，TV與ASIC驗證工程。 內容包含:整合型驗證環境開發，大數據分析與效能改善，BUS Fabric / EMI (External memory interface ) / Low power functions 驗證規劃及執行。 工作中需要設計及精進Verification plan/methodology/bench，對SOC系統有整體而深入的了解。 利用最新EDA tool and concept來完成你的驗證計畫。 工作地點:新竹/台北

## Job Description: - Planning and establishing pass/fail criteria for LEO satellite product testing (e.g., OTA, Thermal Vacuum, Radiation, etc.). - Execution and result analysis of LEO satellite product testing. - Writing test reports and documenting anomalies - Developing and maintaining automated testing programs to improve testing efficiency. ## Skill: - Familiarity with RF or phased array testing is preferred. - Familiarity with Python and basic instrument control is preferred. - Familiarity with military and space testing standards is preferred.

1. IC前期開發階段FPGA與後期ASIC功能驗證, 問題分析與除錯. Function verification/issue clarification during FPGA & ASIC stage of IC developing. 2. 關鍵客戶的問題分析與除錯 Working with key customers to get problems resolved 3. 熟x86系統架構 / 熟協定分析儀, 邏輯分析儀尤佳. Strongly knowledge of x86 architecture/Protocol & Logic analyzer is a plus. 4. 對PCIe/USB/SATA/DisplayPort架構有興趣, 電機電子資工背景無經驗可. Interest in PCIe/USB/SATA/DisplayPort architecture, EE/CS background with no experience are welcome.

Job Title: NPU Modeling Engineer Job Description: Overview: We are seeking an experienced NPU Architect to join our team. As an NPU Architect, you will play a crucial role in designing and implementing the hardware model for our Neural Processing Unit. Your expertise will be instrumental in ensuring efficient and accurate execution of neural network workloads on our NPU. Responsibilities: 1. NPU Architecture Design: • Collaborate with cross-functional teams to define the architecture and specifications for the NPU. • Design the NPU's core components, including the PE array, memory hierarchy, and control logic. • Optimize for performance, power efficiency, and scalability. 2. Bit-True Hardware Model Implementation: • Develop a bit-true hardware model of the NPU in C language. • Ensure that the model accurately represents the NPU's behavior, including arithmetic operations, memory access, and control flow. • Validate the model against reference neural network workloads. 3. Cycle-Accurate Modeling: • Create a cycle-accurate model of the NPU to simulate its behavior at the clock cycle level. • Account for pipeline stages, data dependencies, and timing constraints. • Use tools like Verilog, system-Verilog, or specialized simulation environments to achieve cycle-accurate modeling. 4. Performance Analysis and Optimization: • Profile the NPU model to identify bottlenecks and areas for improvement. • Propose and implement optimizations to enhance performance and reduce latency. • Collaborate with software teams to fine-tune the NPU's behavior. 5. Verification and Validation: • Create testbenches and test vectors to validate both the bit-true and cycle-accurate models. • Conduct functional and performance testing to ensure correctness and compliance with specifications. • Debug and resolve any discrepancies between the models and the actual NPU. 6. Documentation and Communication: • Document the NPU architecture, design decisions, and implementation details. • Present findings, progress, and challenges to stakeholders and management. • Collaborate with software engineers, firmware developers, and system architects. Qualifications: • Master's or Ph.D. degree in Electrical Engineering, Computer Science, or a related field. • Minimum of 3 years of experience in NPU architecture design and implementation. • Proficiency in C/C++/Verilog/System-Verilog programming for hardware modeling. • Familiarity with systolic arrays, matrix multiplication, and neural network accelerators. • Knowledge of bit-true modeling, fixed-point arithmetic, and floating-point arithmetic. • Experience with verification tools and simulation environments. • Strong analytical and problem-solving skills. • Excellent communication and teamwork abilities. • Attention to detail and commitment to quality. If you are passionate about NPU architecture, hardware modeling, and want to be part of a team driving innovation, we encourage you to apply. Join us in shaping the future of AI!

【產品範疇】 MOBILE(手持裝置)驅動晶片 【工作內容】 LCD driver(含OLED) Timing Control數位電路的研發設計與驗證 【需求條件】 1.熟悉HDL coding, simulation, synthesis, and STA flow，有量產經驗尤佳 2.熟悉LCD driver(或OLED)規格，具有相關工作經驗尤佳 3.熟悉Timing Control(Global Timing or SRC control timing or GIP timing)數位電路設計，有相關開發經驗者尤佳

We are looking for a proactive and challenge-driven engineer to join our memory design team. This role primarily focuses on gate-level simulation and functional verification to ensure product quality and alignment with specifications. 【Key Responsibilities】 1. Memory circuit design and verification. 2. Gate-level verilog simulation against to the datasheet. 3. Failure mode analysis. 【Qualifications】 1. Experience in SRAM, DRAM, or other memory product design. 2. Solid understanding of digital circuit design and Verilog HDL. 3. Experience with simulation and debugging, able to work independently. 4. Hands-on experience in failure mode analysis is a plus. 5. Deep RTL design experience is not required, but strong gate-level simulation and verification skills are essential.

RTL design/Verilog behavior model development APR flow support CAD/CAE internal flow/script maintenance

Position Description: 1. To provide key technical support in digital IC design implementation product demonstration, and sales presentations. 2. To demonstrate strong ability and to be hands-on in full APR flow including floorplan, placement, timing analysis, CTS, signoff timing closure methodology. 3. To support key customer engagements on the business increase. 4. Have real design tape-out experience especially for advanced node design. 5. To play a leading role among other team members, while receive little instruction on routine and general assignments. Position Requirements: • Master with 10 years working experience or Bachelor with 12+ years’ experience in IC design. (Cadence Innovus experience will be a plus) • Understanding of full APR flow including timing, congestion analysis and low-power methodology. (Experience for Static Timing Analysis, including SI will be plus) • Good communication in English and Chinese, good confidence and good self-motivation. • Be familiar with shell/perl/tcl etc. script language.

Please apply this role through https://careers.synopsys.com/job/hsinchu/r-and-d-engineering-sr-staff-engineer/44408/84900058096 Synopsys is looking for motivated Product Engineer to help design, develop and test state of the art Static Timing, Characterization and Library modelling tools. The primary focus of the Product Engineer is closely working with R&D team, to influence technologies/solution roadmaps and provide R&D team with accurate input from Field AEs, helping them focus on the most critical design challenges and help define solutions to critical problems. The engineer will work closely with Field AEs, ensuring overall consistency of end-to-end design and analysis flow to meet customer needs. The engineer will also work with Sales and Marketing teams to find and develop new markets, drive new tool evaluations and help customers with the adoption and continuous usage of Static Timing, Characterization and Library Modelling, thus enabling Chip Design customers achieve best Timing, Power and Characterization Goals. Synopsys’ existing and forthcoming tools offer an advanced transistor-level static timing characterization and library modelling solution that addresses the existing and emerging challenges in custom and memory design. They offer predictability and improved productivity to designers. Their concurrent timing, SI features and advanced variation aware analysis enables designers to accurately and quickly identify design issues early-on and avoid expensive late-finding of problems in silicon. Main responsibilities: • Drive new products and new product features that exceed customer needs. • Work with RnD to enable timely implementation of new products and features, and important bug fixes. • Provide consultation to prospective users and/or product capability assessment and validation. • Provide tool trainings to customers and Field AEs. • Provides technical expertise to sales staff through sales presentations and product demonstrations. • Assists the sales staff in assessing potential application of company products to meet customer needs and preparing detailed product specifications for the development and implementation of customer applications/solutions. Requirements: We are looking for an innovative, motivated, and dependable person, with at least BS degree and 8+ years of recent hands-on experience including: · Exceptional expertise in transistor-level analysis and debug circuit level issues for SRAM, RF, ROM memories and Standard Cells. · Good exposure to static timing concepts and CMOS engineering fundamentals. · Good knowledge of TCL and or other scripting languages. · Very good communication, social and leadership skills. Plus: · NanoTime or PrimeLib experience highly desirable.