「數位IC後段APR工程師/技術經理 (新竹)」的相似工作

ASIC Physical / Backend Designer 將負責數位電路的後端實體設計，包括規劃與優化晶片的布局（Floorplan）、電源網格設計（Power Grid Design）、自動布局與繞線（Place and Route）、時脈樹合成（Clock Tree Synthesis）、靜態時序分析（Static Timing Analysis, STA）、物理驗證（Physical Verification）等工作。 主要職責 1. 熟悉以下製程：22nm,16/12nm, 7/5nm Automotive process及其Signoff Criteria. 2. 晶片布局設計：根據Design Specification, Pin Table, Netlist，執行Floorplan規劃及設計。 3. 熟悉Safety Specification Format (SSF)及其實作流程。 4. 時序分析和優化：進行靜態時序分析，熟悉CTS相關技術，確保晶片具備必要的性能，並解決潛在的Timing Violations. 5. 電源架構規劃：熟悉UPF流程，具備Multi-Voltage設計經驗。 6. 功耗分析及優化：熟悉IR分析流程，進行Power Grid優化以符合設計要求。 7. 面積優化：在滿足設計約束條件的前提下，優化晶片布局以達到最小化面積目標。 8. 設計驗證：執行物理驗證(PV)工作，包括DRC（設計規則檢查）、LVS（佈局與網表檢查）等，確保設計符合製造要求。 9. 了解製造相關流程，包括封裝設計和製造約束條件。 10. 與團隊協作：與前/中端設計工程師、製造工程師及測試團隊緊密合作，確保設計符合需求。

1. Analog mixed signal IC layout 2. 熟悉IC Layout tool 3. 熟悉先進製程

1. 負責IC layout的佈局佈線、優化和驗證。 2. 負責部分full custom analog layout的設計和驗證。 3. 確保IC layout符合circuit designer設計需求及DRC/LVS等tapeout signoff

The VLSI Physical Design Engineer is responsible for implementing and optimizing the layout of integrated circuits (ICs) from netlist to GDSII. This role plays a key part in turning high-level logic designs into manufacturable silicon chips, ensuring electrical performance, area, and power (PPA) goals are met, and the physical verification results are good. Key responsibilities: 1. Derive full-chip and block-level physical design from netlist to tape-out (netilst to GDSII). 2. Floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and layout verifications. 3. Work closely with front-end design, DFT, and package teams to ensure design closure. 4. Sign-off on signal integrity, power integrity, reliability and manufacturability including performing static timing analysis (STA), IR drop analysis, EM analysis, and physical verification (DRC/LVS/DFM). 5. Analyze, optimize and resolve congestion, timing, power integrity and signal integrity issues. 6. Create and maintain physical design automation Tcl scripts, and flows development for design implementation. 7. Interface with EDA tool vendors and foundries to ensure design compliance and manufacturability.

(1)Must have BS in CS/EE of relevant experience in IC design field. (2)Familiar with IC design flow, placement and route (P&R), and layout. (3)Circuit knowledge and logic design relevant experience would be a plus.

【工作內容】 • 我們正在尋找具備先進製程經驗的 IC Layout 工程師，加入團隊後可以參與高階SoC /Analog IP 的實體實現，並負責以下工作： -Mixed-Mode FinFET Layout 設計與繪製，確保電路佈局在效能、面積與可靠性之間取得最佳平衡。 -進行 FinFET 製程相關的 DRC / LVS / ERC 驗證，確保設計符合法規與 Foundry 要求。 -熟悉 XRC & EM/IR 分析流程，進行可靠性評估，並針對潛在問題提出改善方案。 【職務條件】 • 必備條件：具備 FinFET 製程經驗，能獨立進行版圖設計與驗證。 -具備類比電路佈局經驗，了解電路特性與佈局考量，能與設計工程師密切合作。 -具備良好的溝通能力與團隊合作精神，能在專案時程內交付高品質成果。

1. Physical design and verification 2. Physical integration 3. Fully layout if necessary

★系統單晶片設計助理工程師 1. 協助執行IC設計前端相關的數位合成 (Tool: Fusion Compiler, Genus) 2. 利用C相關程式優化工作流程 => 同下 3. 協助開發IC => 利用C語言,tcl script工作流程自動化,讓tools自動撈相關report及執行好分析 4. QC => 跑LEC tools確認synthesis合成與RTL是對的 5. C語言 => 須具備寫程式的能力,像基本資料分類,或寫出數學運算公式,利用程式語言方便做大量資料分析 6. 執行STA分析 (Tool: PrimeTime) 7. 協助整理及分析各項report ★ IC 實體設計助理工程師(APR) 1. 在區塊層級的實體實作中進行 R2G（Ready to GDS）流程。 2. 協助進行 DRC（設計規則檢查）/LVS（佈局與電路比對）/ANT（天線效應）/ERC（電氣規則檢查）驗證。 3. 協助 EM（電遷移）/IR（電壓降）結果修正。 4. 負責先進製程（2nm/3nm/4nm）的 Netlist-to-GDS（從電路網表至最終佈局圖）流程： a. 使用 Innovus 完成 floorplan、preCTS、postCTS、postRoute 各階段： 　i. 檢查 floorplan 品質，包括電源架構、SRAM 擺放、端點填充元件（endcap cells）、接地井元件（welltap cells）、電源開關元件（power switch cells）等。 　ii. 檢查 preCTS 階段品質，包括壅塞/溢出情況、元件密度、設定時間違規（setup violation）、漏電比率（leakage ratio）。 　iii. 檢查 postCTS 階段品質，包括壅塞/溢出情況、元件密度、設定/保持時間違規（setup/hold violations）、漏電比率。 　iv. 檢查 postRoute 階段品質，包括 DRC、金屬短路、設定/保持時間違規、漏電比率。 b. 檢查 IR 違規報告並修正： 　i. 分析 IR 違規原因，包括靜態 IR、動態 IR、電源 EMI、訊號 EMI。 　ii. 修正這些違規的方法。 c. 檢查 DRC/LVS 報告並修正： 　i. 分析實體驗證違規原因，包括 DRC、LVS、ANT。 　ii. 修正這些違規的方法。 ★ 員工福利 獎金與補助：提供年終獎金、三節禮金，午餐與晚餐費補助。 保險制度：完善的團體保險保障。 工作氛圍：穩定合作的工作環境，重視員工學習與成長。 員工關懷：定期舉辦員工聚餐與交流活動，增進團隊凝聚力。"

IC layout

【職務內容】 ˙需具備HV經驗 Level Shifter（含 HV Device）、Charge Pump、Source Driver、OpAmp / DAC、TCON（含 Digital Layout + Clock Tree） ˙需具備3-5年Driver相關經驗 ˙需熟悉繞線（Routing） ˙Block-Level設計經驗可 ˙能讀懂 Calibre DRC command file 語法佳 ˙具備28/22nm HV製程經驗佳 ˙無需英文能力，全台灣團隊

負責 3D-IC Interposer 與類比 IP 佈局設計 (Virtuoso / Allegro)，確保電性與實體規格，優化設計流程。 熟悉 Layout tools、Foundry PDK為佳。

投遞網址: https://careers.synopsys.com/job/hsinchu/r-and-d-engineering-sr-engineer/44408/85652406272 You Are: You are an experienced and passionate engineer with a profound curiosity for technology and a strong drive to solve complex problems. With a background in Electrical Engineering, Computer Science, Mathematics, or Physics, you have spent at least a decade mastering your craft, specializing in the intersection of software development and circuit design. Your expertise in C++/C programming, combined with a deep understanding of data structures, algorithms, and circuit simulation, sets you apart as a technical leader. You are comfortable navigating both analog and digital domains, leveraging your circuit design knowledge to drive innovation in electronic design automation (EDA) solutions. What You’ll Be Doing: • Designing, developing, and optimizing SPICE circuit simulation engines to enhance performance and accuracy. • Collaborating with global R&D teams to implement new algorithms and features for circuit analysis and optimization. • Analyzing and resolving challenging functional and performance issues in circuit simulation software. • Providing expert customer support, addressing technical inquiries, and guiding users through complex simulation problems. • Interpreting customer requirements and translating them into technical solutions and product enhancements. • Preparing and delivering technical presentations and documentation to both internal stakeholders and external customers. • Staying current with emerging trends in EDA, circuit simulation, and semiconductor technology to inform product direction. The Impact You Will Have: • Drive continuous improvement in Synopsys’ circuit simulation tools, directly impacting the success of semiconductor innovations worldwide. • Enable customers to achieve faster, more accurate chip designs by delivering robust and reliable simulation solutions. • Enhance the scalability and usability of EDA products, supporting the design of next-generation electronics. • Foster strong customer relationships through exceptional technical support and solution delivery. • Contribute to a collaborative, high-performance R&D culture that values knowledge sharing and creative problem-solving. • Shape the roadmap of Synopsys’ industry-leading simulation technologies through your insights and expertise. What You’ll Need: • MS or PhD in Electrical Engineering, Computer Science, Mathematics, Physics, or a related field. • 10+ years of hands-on experience in software engineering or circuit design. • Strong proficiency in C++ and/or C, with a solid grasp of data structures and algorithms. • Deep understanding of analog and digital circuit design principles. • Proven ability to analyze and resolve complex software or hardware issues independently. • Excellent English communication skills, both written and verbal. Who You Are: • Analytical thinker with a systematic approach to troubleshooting and problem-solving. • Effective collaborator who thrives in diverse, multicultural teams. • Proactive communicator with strong presentation and interpersonal skills. • Adaptable and resilient in the face of technical challenges and evolving priorities. • Detail-oriented, with a passion for delivering high-quality, reliable solutions. • Customer-focused, with a commitment to understanding and meeting user needs. The Team You’ll Be A Part Of: You will join a dynamic and innovative R&D team dedicated to developing advanced SPICE circuit simulation software. Our team brings together experts in software engineering, circuit design, and EDA solutions, working collaboratively across continents to deliver cutting-edge products. We thrive on tackling complex engineering challenges and are committed to continuous learning, knowledge sharing, and supporting each other’s growth. Your contributions will directly influence the capabilities and success of Synopsys’ simulation tools, empowering customers around the world.

1. 負責IC版圖的自動佈局佈線、優化和驗證。 2. 確保IC佈局符合Circuit Designer設計需求及產品、製程、電氣的規範。

我們正在尋找具 2-3年以上經驗的資深版圖工程師，能獨立負責 Analog/Mixed-Signal/SoC IP 及 Top-Level Layout。 需熟悉 layout tool、CMOS 製程與 DRC/LVS 驗證，具高速介面經驗佳。 此職位需規劃 Floorplan、Power/Clock Routing、跨部門協作。 曾參與完整 Tape-out 專案者優先。 職務內容： 1.Interface IP layout 2.Ensure DRC/LVS clean 3.Ensure DRC/LVS clean 4.Fix EM/IR issue 5.Layout environment setup 6.IO planning, placement and routing 7.Help designer to debug and support FIB plan

1.Analog & physical design flow/script development 2.IR/EM sign-off 3.Flip-chip design 4.Physical verification flow

招募導入水處理設備流程中計劃和設計階段裡使用CAD的工程師。 【工作內容】 ■ 接單前的計劃工作 ・應對客戶詢價與會議、系統研究、物料計算、成本計算、流程圖、配置設計、說明書製作、各種文件製作等。 ・優先考慮有志於將來向客戶提案最適合的系統和服務，並引領接單活動的過程工程師。 ・使用Inventor進行設備及設施的設計開發、導入及運營。 ・AutoCAD、Revit等軟體的操作。 ・進行Inventor操作及教育等相關工作。 ・經驗涵蓋流程圖、配置設計、說明製作、管道設計、採購設計、塔槽和機架設計、現場施工問題應對等，未來有機會成為專案設計leader！ 【魅力】 ・AI產業等蓬勃發展，目前半導體需求上升，業績穩定。 ・可以掌握日本半導體相關技術。 【法定項目】 ・勞健保 ・加班費 ・各種休假（特別休假、婚假、喪假、生理假、產檢假、陪產假、產假、育嬰假） ・退休金 【公司福利】 ・餐費津貼 ・員工旅遊（例：泰國） ・升遷制度 ・獎金（一年1次，平均2～3個月左右） ・出差津貼 ・員工聚餐

SOC-NxSOC(next generation) team is hiring both junior and senior engineers, whose work scope is implement methodology development and PPA optimization from RTL to GDS. Join us, you will work together with expertise in all these areas; you will not only work for SOC development, but also enjoy and experience for all related products: smart phone/ tablet/ wearable/automotive etc.; you will work for the most advanced process/technology, the best chip in the world. What you'll be doing: - Methodology development at all stages, including synthesis, PnR, timing, IR, PV etc - PPA optimization What we need to see: - BSEE, MSEE is preferred - Project experience in IC design implementation - Courses taken in circuit design, digital design - Hand-on experience in EDA software from Synopsys (DC/FC-fe/FC-be/ICC2/PT/Formality), Cadence (Innovus), Ansys(Redhawk/RHSC) is preferred Ways to stand out from the crowd: - Proficient user of Perl, Python or TCL is preferred - Excellent English communication skill

1. 負責 FPGA 功能驗證、程式開發、測試、除錯及維護 2. 撰寫 Testbench 進行模擬驗證 3. 具 I2C、SPI 通訊介面運作經驗者 4. 熟悉 Xilinx RFSoc 架構與設計 5. 熟悉 Linux Driver 實作經驗

1. 負責IC佈局和佈線的設計和開發 2. 實現佈局和佈線的細節設計和調整 3. 與相關的團隊成員合作，確保佈局和佈線設計能夠達到高效率和性能 4. 配合其他工程師進行相關的測試、分析和報告 5. 解決相關佈局和佈線問題 6. 修改維護 Command file 7. 使用CADENCE VIRTUOSO或LAKER等工具進行IC佈局和佈線的驗證

1.Analog and mixed mode circuit layout and verification 2.Co-work with designer for layout floor planning,routing and physical verifications 3.command file maintain